isp1582 NXP Semiconductors, isp1582 Datasheet - Page 36

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 40.
ISP1582_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Endpoint Type register: bit allocation
8.3.7 Endpoint Type register (address: 08h)
15
7
-
-
-
-
-
-
Table 39.
The ISP1582 supports all the transfers given in
Rev.
Each programmable FIFO can independently be configured using its Endpoint
MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN
plus OUT) including set-up token buffer, control IN and control OUT, must not exceed
8192 bytes.
This register sets the endpoint type of the indexed endpoint: isochronous, bulk or
interrupt. It also serves to enable the endpoint and configure it for double buffering.
Automatic generation of an empty packet for a zero-length TX buffer can be disabled using
bit NOEMPKT. The register contains 2 bytes, and the bit allocation is shown in
Bit
15 to 13
12 to 11
10 to 0
reserved
2.0”.
14
6
-
-
-
-
-
-
Endpoint MaxPacketSize register: bit description
Symbol
-
NTRANS[1:0]
FFOSZ[10:0]
13
5
-
-
-
-
-
-
Rev. 06 — 20 September 2007
Description
reserved
Number of Transactions: HS mode only.
00 — 1 packet per microframe
01 — 2 packets per microframe
10 — 3 packets per microframe
11 — reserved
These bits are applicable only for isochronous or interrupt
transactions.
FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint.
Applies to both high-speed and full-speed operations.
NOEMPKT
R/W
12
4
0
0
-
-
-
reserved
ENABLE
R/W
11
3
0
0
-
-
-
Ref. 1 “Universal Serial Bus Specification
Hi-Speed USB Peripheral Controller
DBLBUF
R/W
10
2
0
0
-
-
-
R/W
9
1
0
0
-
-
-
© NXP B.V. 2007. All rights reserved.
ENDPTYP[1:0]
ISP1582
Table
R/W
8
0
0
0
-
-
-
36 of 69
40.