s1r72803 Epson Electronics America, Inc., s1r72803 Datasheet - Page 108

• Manufacturer Part Number: s1r72803
• Description: Link/transaction Controller
• Manufacturer: Epson Electronics America, Inc.

S1R72803F00A
9.4.4 CPU Interface Timing
9.4.4.1 CPU Read Cycle
104
Symbol
t
t
t
t
t
CEAC1
RDAC1
t
t
t
t
t
RDD1
RDD2
ACC1
t
t
(Wait input)
RDW
WTS
WTH
t
RDS
RDH
CE1
CE2
P_A [23:0]
AD
P_D[15:0]
*1
P_P30
P_RD_X
P_BCLK
P_CE
t
RDH
X
is formulated according to the earliest signal change (Negate) among P_RD, P_CEx, P_A[23:0]
Address delay time
P_CEx delay time (1)
P_CEx delay time (2)
Wait set-up time
Wait hold time
Read signal delay time (1)
Read data set-up time
Read data hold time
Read signal delay time (2)
Read signal pulse width
Read address access time (1)
Chip enable access time (1)
Read signal access time (1)
Specification
t
AD
t
CE1
C
t
RDD (Only C1)
1
EPSON
C
W
t
CYC
t
(Wait cycle)
WTS
(0.5+WC)–8
*
* WC: Wait cycle signal
Min.
t
t
WTH
29
24
CYC
–
–
–
0
–
0
–
–
–
–
t
t
t
RDW
ACC1
RDA1
=40ns when bus clock is 25MHz in X2 mode.
t
CFAC1
Cn (Last cycle)
t
CYC
t
t
t
CYC
CYC
WTS
(0.5+WC)–20
(1+WC)–20
(1+WC)–20
Max.
t
8
8
8
–
–
8
–
–
8
–
WTH
t
RDS
t
AD
t
RDH
t
t
CE2
RDD2
*1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns