s1r72803 Epson Electronics America, Inc., s1r72803 Datasheet - Page 83

• Manufacturer Part Number: s1r72803
• Description: Link/transaction Controller
• Manufacturer: Epson Electronics America, Inc.

Maintenance Control Register
Bit7..4 Ack Code
Bit3..0 Ack_Parity
IDE Configuration Register
Bit7 UltraDmaMode
Bit6 DmaMode
Bit5 Activate IDE Port
Bit4 Reserved
Bit3 DMARQ_Level
Bit2 Swap
Bit1::0 Reserved
Address Register Name
Address Register Name
0x5F
0x60
When the F_Ack bit is “1”, this register is enabled. When the F_Ack bit is set, an Ack_Code (Ack[7::4]) and
Ack_Parity(Ack[3::0]) specified on this register are transmitted.
Set an arbitrary Ack code.
Set a parity bit for the Ack_Code.
This register sets the mode of operation of the IDE interface of this IC.
When bit6:DmaMode is “1” and bit 7:Ultra Dma Mode is “1”, this bit sets the DMA transfer mode at ULTRA-
DMA.
When bit6:DmaMode is “0”, the setting of this bit is invalid.
Sets the IDE interface transfer mode at DMA or PIO.
DmaMode:1 DMA mode
DmaMode:0 PIO mode
The IDE interface is in all-pin input mode after a reset. By setting this bit at “1”, it is activated.
This bit should be set to “0”.
Decides the level of operation of the HDMARQ signal. Set “0” when using the IDE interface in IDE bus
compatible mode.
DMARQ_Level:1 Negative logic
DMARQ_Level:0 Positive logic
Swaps the higher order 8 bits and lower order 8 bits when using the interface at 16 bits width. The access order
to an address of 0x70 of the IDE-CSO Register is reversed.
SWAP:1 Transfers the higher order 8 bit data first.
SWAP:0 Transfers the lower order 8 bit data first.
IDE_Config0
MaintCtl_L
7: UltraDmaMode
6: DmaMode
5: ActPort
4:
3: DMARQ_Level
2: Swap
1:
0:
7: Ack[7]
6: Ack[6]
5: Ack[5]
4: Ack[4]
3: Ack[3]
2: Ack[2]
1: Ack[1]
0: Ack[0]
Bit Symbol
Bit Symbol
R/W
R/W
R/W
R/W 0:
0: DMA Mode
0: PIO Mode
0: None
0: Positive Logic
0: Nomal
0:
0:
EPSON
Optional AckCode
Description
Description
1: Ultra DMA Mode
1: DMA Mode
1: Negative Logic
1: Swap IDE Port Hi & Lo
1:
1:
1: Active
1:
H.Rst S.Rst B.Rst
H.Rst S.Rst B.Rst
S1R72803F00A
0x00 0x00
0x00 0x00
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