lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 244

• Manufacturer Part Number: lan9312
• Description: Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
14.2.7.2
31:16
15:11
BITS
10:6
5:2
1
0
RESERVED
PHY Address (PHY_ADDR)
These bits select the PHY device being accessed. Refer to
"PHY Addressing," on page 82
assignments.
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY. Refer to
"Ethernet PHY Control and Status Registers," on page 286
descriptions on all PHY registers.
RESERVED
RESERVED
Note:
RESERVED
PHY Management Interface Access Register (PMI_ACCESS)
This register is used to control the management cycles to the PHYs. A PHY access is initiated when
this register is written. This register is used in conjunction with the
Register (PMI_DATA)
Note: This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to
This bit must always be written with a value of 1.
Section 10.2.4, "EEPROM Loader," on page 149
Offset:
to perform write operations to the PHYs.
0A8h
EEPROM Loader
Access Only
DESCRIPTION
for information on PHY address
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
244
Size:
for additional information.
for detailed
Section 7.1.1,
Section 14.4,
32 bits
PHY Management Interface Data
TYPE
WO
WO
WO
RO
RO
RO
SMSC LAN9312
DEFAULT
00000b
00000b
Datasheet
0b
0b
-
-