lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 33

• Manufacturer Part Number: lan9312
• Description: Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
77-79,
PIN
PIN
69
70
82
63
71
Note: For more information on configuration straps, refer to
Note 3.6
System Reset
MDIX Enable
MDIX Enable
Port 1 Auto-
Port 2 Auto-
Purpose I/O
Interrupt
General
Output
NAME
NAME
Strap
Strap
Input
Data
page
in
Table
Configuration strap values are latched on power-on reset or nRST de-assertion.
Configuration strap pins are identified by an underlined symbol name. Some configuration
straps can be overridden by values from the EEPROM Loader. Refer to
"Configuration Straps," on page 40
40. Additional strap pins, which share functionality with the EEPROM pins, are described
Table 3.6 Dedicated Configuration Strap Pins (continued)
3.5.
AUTO_MDIX_1
AUTO_MDIX_2
GPIO[11:8]
SYMBOL
SYMBOL
nRST
IRQ
Table 3.7 Miscellaneous Pins
DATASHEET
IS/OD12/
BUFFER
BUFFER
O8/OD8
Note 3.7
TYPE
TYPE
(PU)
(PU)
(PU)
(PU)
O12
IS
IS
IS
33
for more information.
Port 1 Auto-MDIX Enable Strap: Configures the
Auto-MDIX functionality on Port 1. When latched
low, Auto-MDIX is disabled. When latched high,
Auto-MDIX is enabled.
See
Port 2 Auto-MDIX Enable Strap: Configures the
Auto-MDIX functionality on Port 2. When latched
low, Auto-MDIX is disabled. When latched high,
Auto-MDIX is enabled.
See
General Purpose I/O Data: These general
purpose signals are fully programmable as either
push-pull outputs, open-drain outputs, or Schmitt-
triggered inputs by writing the
Configuration Register (GPIO_CFG)
Purpose I/O Data & Direction Register
(GPIO_DATA_DIR). For more information, refer to
Chapter 13, "GPIO/LED Controller," on page
Note:
Interrupt Output: Interrupt request output. The
polarity, source and buffer type of this signal is
programmable via the
Register
Chapter 5, "System Interrupts," on page
System Reset Input: This active low signal allows
external hardware to reset the LAN9312. The
LAN9312 also contains an internal power-on reset
circuit. Thus, this signal may be left unconnected if
an external hardware reset is not needed. When
used, this signal must adhere to the reset timing
requirements as detailed in
and Configuration Strap Timing," on page
Note:
Note
Note
(IRQ_CFG). For more information, refer to
The remaining GPIO[7:0] pins share
functionality with the LED output pins, as
described in
The LAN9312 must always be read at
least once after power-up or reset to
ensure that write operations function
properly.
3.6.
3.6.
Section 4.2.4, "Configuration Straps," on
DESCRIPTION
DESCRIPTION
Table 3.1
Interrupt Configuration
Section 15.5.2, "Reset
General Purpose I/O
Revision 1.2 (04-08-08)
and
Table
and
Section 4.2.4,
49.
General
445.
3.2.
162.