lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 452

• Manufacturer Part Number: lan9312
• Description: Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
15.5.9
SYMBOL
t
cycle
t
t
t
A[2], END_SEL
t
t
t
asu
dsu
csh
csl
ah
dh
FIFO_SEL
nCS, nWR
TX Data FIFO Direct PIO Write Cycle Timing
Please refer to
description of this mode.
Note: A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The
D[31:0]
Write Cycle Time
nCS, nWER Assertion Time
nCS, nWR De-assertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR De-assertion
Data Hold Time
cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de-
asserted in any order.
Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values
Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing
Section 8.4.9, "TX Data FIFO Direct PIO Writes," on page 111
DESCRIPTION
t
asu
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
452
t
csl
t
t
cycle
dsu
MIN
45
32
13
0
0
7
0
t
dh
t
ah
TYP
t
csh
MAX
for a functional
SMSC LAN9312
Datasheet
UNITS
nS
nS
nS
nS
nS
nS
nS