lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 305

• Manufacturer Part Number: lan9312
• Description: Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.4.2.11
BITS
15:8
7
6
5
4
3
2
1
0
RESERVED
INT7
This interrupt source bit indicates when the ENERGYON bit of the
PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
has been set.
0: Not source of interrupt
1: ENERGYON generated
INT6
This interrupt source bit indicates Auto-Negotiation is complete.
0: Not source of interrupt
1: Auto-Negotiation complete
INT5
This interrupt source bit indicates a remote fault has been detected.
0: Not source of interrupt
1: Remote fault detected
INT4
This interrupt source bit indicates a Link Down (link status negated).
0: Not source of interrupt
1: Link Down (link status negated)
INT3
This interrupt source bit indicates an Auto-Negotiation LP acknowledge.
0: Not source of interrupt
1: Auto-Negotiation LP acknowledge
INT2
This interrupt source bit indicates a Parallel Detection fault.
0: Not source of interrupt
1: Parallel Detection fault
INT1
This interrupt source bit indicates an Auto-Negotiation page received.
0: Not source of interrupt
1: Auto-Negotiation page received
RESERVED
Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)
This read-only register is used to determine to source of various Port x PHY interrupts. All interrupt
source bits in this register are read-only and latch high upon detection of the corresponding interrupt
(if enabled). A read of this register clears the interrupts. These interrupts are enabled or masked via
the
Port x PHY Interrupt Mask Register
Index (decimal): 29
DESCRIPTION
DATASHEET
(PHY_INTERRUPT_MASK_x).
305
Size:
16 bits
Port x
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
TYPE
RO
RO
Revision 1.2 (04-08-08)
DEFAULT
0b
0b
0b
0b
0b
0b
0b
-
-