uja1076tw/5v0/wd NXP Semiconductors, uja1076tw/5v0/wd Datasheet - Page 37
uja1076tw/5v0/wd
Manufacturer Part Number
uja1076tw/5v0/wd
Description
High-speed Can Core System Basis Chip
Manufacturer
NXP Semiconductors
Datasheet
1.UJA1076TW5V0WD.pdf
(45 pages)
- Current page: 37 of 45
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NXP Semiconductors
Table 10.
T
with respect to ground; positive currents flow in the IC; typical values are given at V
[1]
[2]
[3]
UJA1076_1
Product data sheet
Symbol
Oscillator
f
osc
vj
=
A system reset will be performed if the watchdog is in Window mode and is triggered less than t
period (or in the first half of the watchdog period).
The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see
Window mode only.
The watchdog will be reset if it is in window mode and is triggered at least t
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
−
trig(wd)2
40 °C to +150
after the start of the watchdog period (watchdog overflows).
Dynamic characteristics
Parameter
oscillator frequency
°
C; V
BAT
Fig 15. Timing test circuit for CAN transceiver
Fig 16. Timing diagram CAN transceiver
= 4.5 V to 28 V; V
V
O(dif)bus
V
V
V
V
CANH
RXDC
TXDC
CANL
…continued
C RXDC
10 %
90 %
BAT
t
t
d(TXDCL-RXDCL)
Rev. 01 — 1 December 2009
d(TXDC-busdom)
Conditions
50 %
> V
V1
RXDC
TXDC
90 %
10 %
; V
BAT
50 %
> V
SBC
GND
BAT
V2
; R
trig(wd)1
(CANH-CANL)
CANH
CANL
High-speed CAN core system basis chip
, but not more than t
10 %
90 %
50 %
t
BAT
d(TXDCH-RXDCH)
t
= 45
d(TXDC-busrec)
R CANH − R CANL
= 14 V; unless otherwise specified.
90 %
10 %
Ω
trig(wd)1
to 65
015aaa079
Min
460.8
trig(wd)2
after the start of the watchdog
Ω
; all voltages are defined
50 %
Table
, after the start of the
C CANH − C CANL
Typ
512
UJA1076
© NXP B.V. 2009. All rights reserved.
4); valid in watchdog
015aaa080
Max
563.2
5 V
3.6 V
1.4 V
0 V
2.2 V
−3.2 V
−5 V
37 of 45
Unit
kHz
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