w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 54

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

12. TIMER
The Keyboard controller has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each
timer or pre-scalar is given by 1/n + 1, where n is the value in the corresponding timer or pre-scalar
latch. All timers are count down. When the timer reaches "00H", an underflow occurs at the next count
pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a
timer underflow, the corresponding interrupt request bit is set to 1.
12.1 Timer 1 and Timer 2
The count source of pre-scalar 12 is the oscillator frequency divided by 16. The output of pre-scalar 12
is counted for both timer 1 and 2, and a timer underflow sets the interrupt request bit.
12.2 Timer X and Timer Y
Timer X and Timer Y can works in one of four operating modes by setting the timer XY mode register.
12.2.1 Timer Mode
The Timer X only counts f(XIN)/16.
The Timer Y can select the count by f(Xin)/16 or f(Xcin).
12.2.2 Pulse Output Mode
Timer X or timer Y counts f(XIN)/16. Whenever the contents of the timer reach “00H”, the signal output
from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is 0, the
pin is “H” after initial. If it is 1, the pin is “L” after initial.
When using a timer in this mode, set the corresponding direction register of port GP54 (or GP55) to
output mode. Also, set timer to this mode may result in the GPIO (GP54, 55) malfunctioned.
12.2.3 Event Counter Mode
Operating on event counter mode is the almost same as in timer mode, except that the timer counts
signals input through the CNTR0 or CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit
is 0, the rising edge on the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active
edge selection bit is 1, the falling edge on the CNTR0 (or CNTR1) pin is counted.
12.2.4 Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is 0, the timer counts f(XlN)/I 6 while the CNTR0 ( or
CNTR1) pin is H. If the CNTR0 (or CNTR1) active edge selection bit is 1, the timer counts while the
CNTR0 (or CNTR1) pin is L.
Bit 0: PWM2 output enable
= 0 disable PWM3 output
= 1 enable PWM3 output
= 0 disable PWM2 output
= 1 enable PWM2 output
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Publication Release Date: June 23, 2003
W83L950D
Revision 1.0