w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 96

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

22.9 Auxiliary SMBus Host/Slave interrupt Status Register (AISR)
Note: After Slave Address Match (bit 5 of AISR) set, the data ready (bit 6 of AISR) will be set after 1
clock.
Advanced SFR Address
Default Value
Attribute:
7
6
5
4
3
2
1
0
Bit
Reserved.
Receive Data Ready Interrupt (RXDATARDY_I).
1 = Indicates the receive FIFO data is ready. Write 1 to clear this bit.
Host Slave Address Match Interrupt (ADDRMATCH_I).
1 = Host slave SMBus device has detected the matched address. Write 1 to clear this bit.
Note: The bit will be set when received Slave Address + Write or Slave Address + Read.
Master/Slave Receiver Package End Interrupt (RXEND_I).
1 = The SMBus package has a grace Read Stop which is NOT ACK to respond the slave
and hardware STOP is finished. Write 1 to clear this bit.
Host Status Interrupt (HSTATUS_I).
1 = When SMBus fail, collision, or device error is detected by the SMBus controller. Write 1
to clear this bit.
Note: The HSR details error status bits.
Transmitter Empty Interrupt Status (TXEMP_I).
1 = When transmitter Data FIFO is empty. Write 1 to clear this bit.
Transmitter Threshold Level Interrupt (TXTHL_I).
1 = The transmitter FIFO is below the threshold level. Write 1 to clear this bit.
Receiver Threshold Level Interrupt (RXTHL_I).
1 = The receiver FIFO is over the threshold level. Write 1 to clear this bit.
0x30
0x00
Read/Write
Description
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Publication Release Date: June 23, 2003
W83L950D
Revision 1.0