sta333bwqs13tr STMicroelectronics, sta333bwqs13tr Datasheet - Page 41

• Manufacturer Part Number: sta333bwqs13tr
• Description: 2.1-channel High-efficiency Digital Audio System With Qsound Qhd
• Manufacturer: STMicroelectronics

STA333BWQS
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
Binary output mode clock loss detection
Table 47.
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
Table 48.
Actively prevents double trigger of LRCLK.
Auto EAPD on clock loss
Table 49.
When active, issues a power device power down signal (EAPD) on clock loss detection.
IC power down
Table 50.
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power-stage, then the master clock to all internal hardware expect the
I
External amplifier power down
Table 51.
The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0,
the internal power section is placed on a low-power state (disabled). This register also
controls the DDX4B/EAPD output pin when OCFG = 10.
2
C block is gated. This places the IC in a very low power consumption state.
Bit
Bit
Bit
Bit
Bit
3
4
5
7
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Binary output mode clock loss detection
LRCK double trigger protection
Auto EAPD on clock loss
IC power down
External amplifier power down
RST
RST
RST
RST
RST
1
1
0
1
0
PWDN
Name
Name
Name
Name
Name
EAPD
BCLE
ECLE
LDTE
Binary output mode clock loss detection enable
LRCLK double trigger protection enable
Auto EAPD on clock loss
0: IC power down low-power condition
1: IC normal operation
0: external power stage power down active
1: normal operation
Description
Description
Description
Description
Description
Register description
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