tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 59

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

with defined settings at a defined state. Otherwise the state machine may hang up.
Reconfigurations in HOLD Mode are faster, because there is no Start-Up sequence.
The following flowchart and explanation show and help to understand the internal
behavior of the Finite State Machine (FSM) in Run Mode Slave.
Figure 37
2.6.1.3
This state (item 4 in
Slave. HOLD state can be reached after the Start-Up Sequencer and Initialization of the
chip have been completed and the chip is working in state 3. To reconfigure the chip the
SFR control bit HOLD must be set. After reconfiguration in this state the SFR control bit
HOLD must be cleared again. After leaving the HOLD state, the INIT state is entered and
the receiver can work with the new settings. Be aware that the time between changing
the configuration and reinitialization of the chip has to be at least 40us. Take note that
one SPI command for clearing the SFR control bit HOLD needs 24 bits or 12μs at an SPI
data rate of 2.0Mbit/s. The remaining 28μs must be guaranteed by the application.
Figure 38
Data Sheet
SPI Command
FSM State
4
reconfiguration
Ready for
Hold
HOLD Mode
Instruction
Hold == 0
Run Mode Slave
HOLD State Behavior (INITPLLHOLD disabled)
Data available at Port Pin
Write
0x02
Address
CMC0
Figure
Hold == 1
HOLD=1
Data
37) is used for fast reconfiguration of the chip in Run Mode
Instruction
Write
0x02
x_CHCFG/
Address
x_PLL..
(sel. other
channel)
Data
59
1
2
3
HOLD
Wait Till Startup
Data Available
Has Finished
Receive
At Port Pin
Wait
INIT
40us
Instruction
Write
0x02
Startup Finished == 1
Functional Description
12us @ 2. 0MHz
Address
CMC0
HOLD=0
Operating Mode
Data
No Change in
Startup Finished == 0
V1.0, 2010-02-19
INIT
TDA5225
available at
Port Pin
Data