tda5235 Infineon Technologies Corporation, tda5235 Datasheet - Page 89

• Manufacturer Part Number: tda5235
• Description: Enhanced Sensitivity Double-configuration Receiver With Digital Baseband Processing
• Manufacturer: Infineon Technologies Corporation

2.5.5
The control interface used for device control and data transmission is a 4-wire SPI
interface.
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•
•
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Level definition:
logic 0 = low voltage level
logic 1 = high voltage level
Note for non-Burst modes: It is possible to send multiple frames while the device is
selected. It is also possible to change the access mode while the device is selected by
sending a different instruction.
Note: In all bus transfers MSB is sent first, except for the received data read from the
FIFO. There the bit order is given as first bit received is first bit transferred via the bus.
To read from the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
data byte at this address is then shifted out on SDO. After completing the read operation,
the master sets the NCS line to high.
Figure 59
Data Sheet
SDO
NCS
SCK
SDI
NCS
SDI
SDO
SCK
on SDO at falling SCK edges.
high impedance Z
I7 I6
1
I5 I4
Instruction
- select input, active low
- data output
- data input
- clock input: Data bits on SDI are read in at rising SCK edges and written out
Digital Control (4-wire SPI Bus)
I3 I2
Read Register
I1 I0
8
A7 A6
1
Register Address
A5 A4
Frame
A3 A2 A1 A0
8
D7 D6 D5 D4
1
Data Out
D3 D2 D1
D0
8
89
I7 I6
1
I5 I4
Instruction
I3 I2 I1 I0
8
A7 A6
1
Register Address
A5 A4
Frame
A3 A2 A1 A0
Functional Description
8
D7 D6 D5 D4
1
V1.0, 2010-02-19
Data Out
D3 D2 D1 D0
TDA5235
8