lm2512 National Semiconductor Corporation, lm2512 Datasheet - Page 12

• Manufacturer Part Number: lm2512
• Description: Mobile Pixel Link Level 0, 24-bit Rgb Display Interface Serializer With Dithering And Look Up Table Option
• Manufacturer: National Semiconductor Corporation

www.national.com
LOOK UP TABLE OPTION AND SPI INTERFACE
Three 256 X 8-bit SRAMs provide a Look Up Table for inde-
pendent color correction. The LUT is disabled by default and
also after a device PD* cycle. The PD* cycle can be entered
via the PD* input pin directly, or by stopping the PCLK. Before
using the LUT, the SRAM must be loaded with its contents. If
power is cycled to the device, the LUT must be loaded again.
To enable the LUT:
1.
2.
3.
4.
5.
When waking up the LM2512 from the power down mode
(PD*=L), the LUT needs to be enabled if it is desired. Contents
to the SRAM are still held and valid.
1.
16-bit READ
The 16-bit READ is shown in 16-bit READ – SPI. The SDA
payload consists of a "1" (Read Command), seven address
bits and eight data bits which are driven from the device. The
PAGE WRITE
The PAGE WRITE is shown in Figure 17. The SDA payload
consists of a "0" (Write Command), seven address bits of the
start address and then the consecutive data bytes. 256 bytes
maximum can be sent. The CSX signal is driven Low, and the
There are three SPI Interface signals: CSX - SPI Chip Select,
SCL - SPI Clock, and SDA - SPI Data. CSX and SCL are
inputs on the LM2512. SDA is a bi-directional Data line and
is an input for a WRITE and an output for the READ_DATA
portion of a READ operation. READs are optional and are not
Select/Unlock the LM2512 SPI Interface - Write FF’h to
REG22 (16’h)
Write the LUT contents to the SRAM using Writes or
Page Writes
Access each of the three SRAM at least once to ensure
that they are in their lowest power state.
Enable the LUT - Write a 01’h to REG0 (00’h)
De-Select/Lock the LM2512 SPI interface -Write 00’h to
REG22 (16’h)
Select/Unlock the LM2512 SPI Interface - Write FF’h to
REG22 (16’h)
Bit
SDA 0
Bit
SDA 1
Bit
SDA 0
B15
B15
B15
D7
(Data Byte 1)
B14
A6
B14
A6
B14
A6
(start address)
D6
B13
A5
B13
A5
B13
A5
D5
B12
A4
B12
A4
B12
A4
D4
B11
A3
B11
A3
B11
A3
D3
B10
A2
B10
A2
B10
A2
D2
16-bit WRITE – SPI
B9
A1
B9
A1
B9
A1
D1
16-bit READ – SPI
PAGE WRITE
B8
A0
B8
A0
B8
A0
D0
12
2.
3.
4.
If power is cycled to the device, the LUT SRAMs must be
loaded again.
SPI Interface
The Serial Peripheral Interface (SPI) allows control over var-
ious aspects of the LM2512, the Look Up Table operation,
and access to the three 256 x 8-RAM blocks. There are 9
defined registers in the device. Three SPI transactions are
supported, which are: 16-bit WRITE, PAGE WRITE, and a 16-
bit READ. The SPI interface is disabled when the device is in
the sleep mode (via PCLK Stop or by PD* = L). The SPI in-
terface may be used when PD* = H.
16-bit WRITE
The 16-bit WRITE is shown in 16-bit WRITE – SPI. The SDA
payload consists of a "0" (Write Command), seven address
bits and eight data bits. The CSX signal is driven Low, and
16-bits of SDA (data) are sent to the device. Data is latched
on the rising edge of the SCL. After each 16-bit WRITE, CSX
must return HIGH.
CSX signal is driven Low, and the host drives the first 8 bits
of the SDA ("1" and seven address bits), the device then
drives the respective 8 bits of the data on the SDA signal.
host drives the SDA signal with a "0" (Write Command), the
seven start address bits and the variable length data bytes.
The Page Write is denoted by the CSX signal staying low
while the data bytes are streamed. Data is latched on the ris-
ing edge of the SCL.
required. Due to the Select/Unlock – De-Select/Lock feature
of the device the SPI interface may be shared with the display
driver. Several connection configurations are possible. A cou-
ple examples are shown in Figure 13 and Figure 14.
B7
D7
B7
D7
B7
D7
(Data Byte 0)
D7
(Data Byte n, 256 max.)
Enable the LUT - Write a 01’h to REG0 (00’h)
Optional -select Lane Scale if not using default
De-Select/Lock the LM2512 SPI interface -Write a 00’h
to REG22 (16’h)
B6
D6
B6
D6
B6
D6
D6
B5
D5
B5
D5
B5
D5
D5
B4
D4
B4
D4
B4
D4
D4
B3
D3
B3
D3
B3
D3
D3
B2
D2
B2
D2
B2
D2
D2
B1
D1
B1
D1
B1
D1
D1
B0
D0
B0
D0
B0
D0
D0