lm2512 National Semiconductor Corporation, lm2512 Datasheet - Page 18

• Manufacturer Part Number: lm2512
• Description: Mobile Pixel Link Level 0, 24-bit Rgb Display Interface Serializer With Dithering And Look Up Table Option
• Manufacturer: National Semiconductor Corporation

www.national.com
LM2512 Operation
POWER SUPPLIES
The V
same potential between 1.6V and 2.0V. V
logic interface and may be powered between 1.6V and 3.0V
to be compatible with a wide range of host and target devices.
V
or before. V
BYPASS RECOMMENDATIONS
Bypass capacitors should be placed near the power supply
pins of the device. Use high frequency ceramic (surface
mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF Tan-
talum capacitor is recommended near the SER V
PLL bypass. Connect bypass capacitors with wide traces and
use dual or larger via to reduce resistance and inductance of
the feeds. Utilizing a thin spacing between power and ground
planes will provide good high frequency bypass above the
frequency range where most typical surface mount capacitors
are less effective. To gain the maximum benefit from this, low
inductance feed points are important. Also, adjacent signal
layers can be filled to create additional capacitance. Minimize
loops in the ground returns also for improved signal fidelity
and lowest emissions.
UNUSED/OPEN PINS
Unused inputs must be tied to the proper input level—do not
float them.
PHASE-LOCKED LOOP
A PLL is enabled to generate the serial link clock. The Phase-
locked loop system generates the serial data clock at 4X or
6X of the input clock depending upon the number of MD Lanes
selected. The MC rate is limited to 80 MHz for this enhanced
Class 0 MPL PHY.
POWER DOWN/OFF CONFIGURATION / OPTIONS AND
CLOCK STOP
The LM2512 (SER) can be controlled by it’s PD* input pin or
via a auto power down mode that monitors the PCLK input
signal.
For PD* Input Power Down control, a GPO signal from the
host is used to enable and disable the LM2512 and the DES.
The LM2512 is enabled when the PD* input is High and dis-
abled when the PD* input is Low.
When using the auto power down mode, the PD* input needs
to be held High. When the PCLK is held static, the SER will
detect this condition and power down. When the PCLK is
restarted, the SER powers up, The DES is calibrated, and the
PLL locks to the incoming clock signal. Once this is complete,
video data transmission can occur. See Figures 3, 4 and Fig-
ure 9. The stopping of the pixel clock should be done cleanly.
The minimum clock stop gap should be at least 4 PCLK cycles
wide. Floating of the PCLK input pin is not recommended.
Consult the MPL DES datasheet to determine requirements
that the DES requires.
Application Information
SYSTEM BANDWIDTH CALCULATIONS
For a HVGA (320 X 480) application with the following as-
sumptions: 60 Hz +/−5% refresh rate, 10% blanking,
RGB666, and 2 MD Lanes and following calculations can be
made:
DD
/V
DDA
DD
and V
should be powered ON at the same time as V
DDIO
DDA
then V
(MPL and PLL) must be connected to the
DD
/V
DDA
is not recommended.
DDIO
powers the
DDA
pin for
DDIO
18
Calculate PCLK - 320 X 480 X 1.1 X 60 X 1.05 = 10.6 MHz
PCLK
Calculate MC rate - since the application is 2 MD lanes, PCLK
X 6 is the MC rate or 63.87 MHz. Also check that this MC rate
does not exceed the MC maximum rate for the chipset.
Calculate MD rate - MPL uses both edges of the MC to send
serialized data, thus data rate is 2X the MC rate, or 127.7
Mbps per MD lane in our example.
Calculate the application throughput - using 2 MD lanes,
throughput is 2 X of the MD rate or 255.5 Mbps of raw band
width.
For a VGA (640 X 480) application with the following assump-
tions: 55 Hz +/−5% refresh rate, 10% blanking, RGB666, and
3 MD Lanes and following calculations can be made:
Calculate PCLK - 640 X 480 X 1.1 X 55 X 1.05 = 19.5 MHz
PCLK
Calculate MC rate - since the application is 3 MD lanes, PCLK
X 4 is the MC rate or 78.1 MHz. Also check that this MC rate
does not exceed the MC maximum rate for the chipset.
Calculate MD rate - MPL uses both edges of the MC to send
serialized data, thus data rate is 2X the MC rate, or 156 Mbps
per MD lane in our example.
Calculate the application throughput - using 3MD lanes,
throughput is 3X of the MD rate or 468 Mbps of raw band
width.
SYSTEM CONSIDERATIONS
When employing the MPL SER/DES chipset in place of a
parallel video bus, a few system considerations must be taken
into account. Before sending video data to the display, the
SER/DES must be ready to transmit data across the link. The
MPL link must be powered up, and the PLL must be locked
and the DES calibrated.
FLEX CIRCUIT RECOMMENDATIONS
The MPL lines should generally run together to minimize any
trace length differences (skew). For impedance control and
also noise isolation (crosstalk), guard ground traces are rec-
ommended in between the signals. Commonly a Ground-
Signal-Ground (GSGSGSG) layout is used. Locate fast edge
rate and large swing signals further away to also minimize any
coupling (unwanted crosstalk). In a stacked flex interconnect,
crosstalk also needs to be taken into account in the above
and below layers (vertical direction). To minimize any cou-
pling locate MPL traces next to a ground layer. Power rails
also tend to generate less noise than LVCMOS so they are
also good candidates for use as isolation and separation.
The interconnect from the SER to the DES typically acts like
a transmission line. Thus impedance control and ground re-
turns are an important part of system design. Impedance
should be in the 50 to 100 Ohm nominal range for the
LM2512. Testing has been done with cables ranging from 40
to 110 Ohms without error (BER Testing). To obtain the
impedance, adjacent grounds are typically required ( 1 layer
flex), or a ground shield / layer. Total interconnect length is
intended to be in the 20cm range, however 30cm is possible
at lower data rates. Skew should be less than 500ps to max-
imize timing margins.
GROUNDING
While the LM2512 employs three separate types of ground
pins, these are intended to be connected together to a com-
mon ground plane. The separate ground pins help to isolate
switching currents from different sections of the integrated
circuit (IC). Also required is a nearby signal return (ground)
for the MPL signals. These should be provided next to the
MPL signals, as that will create the smallest current loop area.