lm2512 National Semiconductor Corporation, lm2512 Datasheet - Page 9

• Manufacturer Part Number: lm2512
• Description: Mobile Pixel Link Level 0, 24-bit Rgb Display Interface Serializer With Dithering And Look Up Table Option
• Manufacturer: National Semiconductor Corporation

OFF (O)
LINK-UP (LU)
Active (A)
SERIAL BUS TIMING
Data valid is relative to both edges of a RGB transaction as
shown in Figure 8. Data valid is specified as: Data Valid before
Clock, Data Valid after Clock, and Skew between data lines
should be less than 500ps.
Notes on MC/MD Line State:
0 = no current (off)
L = Logic Low—The higher level of current on the MC and MD lines
H = Logic High—The lower level of current on the MC and MD lines
X = Low or High
A = Active Clock
SERIAL BUS START UP TIMING
In the Serial Bus OFF phase, SER line drivers for MDs and
MC are turned off such that zero current flows over the MPL
lines. On the SER side, when the PD* input pin is de-asserted
(driven High), or with PD* = High and the PCLK is turned on,
the SER will power up its bias block during t0.
The SER will next drive the MC line to the logic Low (5I cur-
rent) state for 200 PCLK cycles (t1). The DES devices detects
the current flowing in the MC line, and powers up its analog
circuit blocks (or alternately is controlled by its PD* input pin
- device specific).
The SER then drives the MC line to a logic High (1I current)
for 20 PCLK cycles (t2). On the MC low-to-high transition, the
FIGURE 7. Three MD Lane MPL Interface
Name
MC State
0LHL
A
0
MDn State
20172802
000L
X
0
TABLE 1. Link Phases
Link is Off
Start Up Pulse
Streaming Data
9
Phase Description
SERIAL BUS PHASES
There are three bus phases on the MPL serial bus. These are
determined by the state of the MC and MD lines. The MPL
bus phases are shown in Table 1.
The LM2512 supports MPL Level 0 Enhanced Protocol with
a Class 0 PHY.
DES samples the current and optimizes it current sources to
match that of the drivers.
The MC is now driven to a logic Low (5I current) for 8 PCLK
cycles (t3).
Next the SER PLL is locked to the PCLK. A hold off counter
of 600 PCLK cycles is used to hold off until the PLL has locked
and is stable (t4). At this point, streaming RGB information is
now sent across the MPL link.
Link-Up is shown in Figure 9. The MC and MDn signals are
current waveforms. Data at the DES output will appear a la-
tency delay later.
FIGURE 8. Dual Link Timing
Pre-Phase
A, or LU
LU
O
20172803
www.national.com
Post-Phase
A or O
LU
O