lm2512 National Semiconductor Corporation, lm2512 Datasheet - Page 8

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lm2512

Manufacturer Part Number
lm2512
Description
Mobile Pixel Link Level 0, 24-bit Rgb Display Interface Serializer With Dithering And Look Up Table Option
Manufacturer
National Semiconductor Corporation
Datasheet

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Functional Description
The LM2512 is a Mobile Pixel Link (MPL) Serializer that se-
rializes a 24-bit RGB plus three control signals (VS, HS, and
DE) to two or three MPL MD lines plus the serial clock MC.
The 24-bit RGB data is dithered to 18 bits by the Serializer.
BUS OVERVIEW
The LM2512 is a multi-lane MPL Serializer that supports a 24-
bit RGB source interface. The MPL physical layer is purpose-
built for an extremely low power and low EMI data transmis-
sion while requiring the fewest number of signal lines. No
external line components are required, as termination is pro-
vided internal to the MPL receiver. A maximum raw through-
put of 480 Mbps (3-lane raw) is possible with this chipset. The
MPL interface is designed for use with common 50Ω to
100Ω lines using standard materials and connectors. Lines
may be microstrip or stripline construction. Total length of the
interconnect is expected to be less than 20cm.
FIGURE 6. General LM2512 Block Diagram
FIGURE 5. SPI Interface
8
An optional Look Up Table consisting of three 256 X 8-bit
RAMs may also be used and is controlled via a 3-wire SPI
interface. The LM2512 is compatible with certain discrete
MPL Deserializers and also Display Drivers with integrated
MPL Deserializers.
20172892
20172894

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