pxb4360f Infineon Technologies Corporation, pxb4360f Datasheet - Page 32

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pxb4360f

Manufacturer Part Number
pxb4360f
Description
Content Addressable Memory Element Came
Manufacturer
Infineon Technologies Corporation
Datasheet

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These registers contain a complete entry consisting of PN/VPI/VCI, the P_IP flag and the VCON
flag. The read data contained in the CAME memory line, selected with the DLCI register
contents, is transferred to these registers. At the end of a read request #5, the ALP can read the
resulting data from the RPN,RVPI,RVCI,RI,RV registers.
Read Address 1
Value after reset undefined
Data Sheet
16-Bit Mode
32-Bit Mode
Valid Connection flag:
0
1
Path Intermediate Point flag:
0
1
request 5:
request 5:
H
, 6
PN(3:0)
H
Connection not valid.
Connection valid.
Address reduction is performed over PN / VPI / VCI.
Path Intermediate Point; address reduction is performed only over
PN / VPI.
, 9
H
1
6
9
1
6
H
H
H
H
H
for VCON, P_IP
for VCI(15:0)
for VCON, P_IP
for PN(3:0), VPI(11:0)
for PN(3:0), VPI(11:0), VCI(15:0)
VCI(15:8)
VCI(7:0)
VPI(7:0)
5-32
VPI(11:8)
VCON
P_IP
07.2000

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