pxb4360f Infineon Technologies Corporation, pxb4360f Datasheet - Page 46

• Manufacturer Part Number: pxb4360f
• Description: Content Addressable Memory Element Came
• Manufacturer: Infineon Technologies Corporation

For more demanding applications, two CAME chips can be cascaded to build up one virtual
device with double capacity and the identical physical bus interface to an external controller. The
Cascade Interface is used for this purpose and consists of the CO(2..0) outputs and the CI(2..0)
and CA inputs as shown in
Both CAME chips receive the same requests from ALP. Depending on the request, the
determination of which chip may answer at the end of the request is either known in advance
(read, write and test requests #4..6) or results from the operation (search requests #1..3). In the
second case, the master must inform the slave of its search result and indicate whether or not it
processes the search request. The same report takes place from the slave to the master. This
is done with the signals CO(1..0). Processing the crosswise transferred status information is
done according to
the CO(1..0) signals at this time is done according to
In order to avoid bus conflicts on reading of cascaded CAME chips, the master has the
opportunity to disable data output of the slave CAME using the CO(2) signal. This signal is
important in case of a parity error, for example.
The CO(2..0) outputs must be connected to the CI(2..0) inputs of the opposite CAME.
Data Sheet
ALP
a) Single CAME application
Bus
interface
CAME
CO(0)
CO(1)
CO(2)
. The timing of this transfer is defined in
CI( 0)
CI( 1)
CI( 2)
CA
1k
.
GND
ALP
6-46
a) 2 CAME application
.
Bus
interface
Bus
interface
(Master)
(Slave)
CAME
CAME
CI(2:0)
CO(2:0)
CI(2:0)
CO(2:0)
CA
CA
. The interpretation of
10k
1k
+ 3.3 V
GND
07.2000