pdi1394l41 NXP Semiconductors, pdi1394l41 Datasheet
pdi1394l41
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pdi1394l41 Summary of contents
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... SEE THE LAST 2 PAGES OF THIS DATASHEET FOR A LIST OF ERRATA RELATED TO THIS PART. NOTICE: DTLA SENSITIVE INFORMATION HAS BEEN WITHHELD FROM THIS DATA SHEET. SEE SECTION 2.1 FOR DETAILS. PDI1394L41 1394 content protection AV link layer controller Preliminary specification Supersedes data of 2000 Apr 15 hilips ...
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... Preliminary specification PDI1394L41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Preliminary specification PDI1394L41 . . . . . . . . . . . . . . . . . . . . . . ...
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... Both 8 bit and 16 bit wide data paths, as well as multiplexed/non-multiplexed access modes are supported. The PDI1394L41 is powered by a single 3.3 V power supply and the inputs and outputs are 5 V tolerant available in the LQFP144 package. 2.1 Use restrictions ...
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... RESERVED 104 AV1EMIO 69 GND 105 AV1EMI1 70 V 106 GND DD 71 RESERVED 107 RESERVED 108 AV1D0 2 Preliminary specification PDI1394L41 Pin Function 109 AV1D1 110 AV1D2 111 AV1D3 112 GND 113 V DD 114 AV1D4 115 AV1D5 116 AV1D6 117 AV1D7 118 AV1READY ...
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... AV2ERR1/DATAINV 12KB BUFFER LINK CORE MEMORY (ISOCH & ASYNC PACKETS) ASYNC TRANSMITTER AND RECEIVER CONTROL AND STATUS REGISTERS 3 Preliminary specification PDI1394L41 SV01021 CYCLEOUT LPS CYCLEIN PHY D[0:7] PHY CTL[0:1] LREQ LinkOn ISON PD SCLK 1394MODE NOTE: THERE IS ONE ISOCHRONOUS RECEIVER AND ONE ISOCHRONOUS TRANSMITTER— ...
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... Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control and status registers. Write enable. When asserted (LOW) in conjunction with HIF CSN, a write to the PDI1394L41 internal registers is requested. (NOTE: HIF WRN and HIF RDN : if these are both LOW in conjunction with HIF CSN, then a write cycle takes place ...
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... The AV1READY signal should be processed by the sink through one level of pipelining, which means that the receiver must be able to accept data on the cycle in which AV1READY is de-asserted. The receiving interface does not have to accept data on the cycle in which AV1READY is asserted. 5 Preliminary specification PDI1394L41 ...
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... The AV2READY signal should be processed by the sink through one level of pipelining, which means that the receiver must be able to accept data on the cycle in which AV2READY is de-asserted. The receiving interface does not have to accept data on the cycle in which AV2READY is asserted. 6 Preliminary specification PDI1394L41 ...
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... The isochronous transmit FIFO is not receiving data for transmission 2. The isochronous transmitter is disabled 3. No asynchronous packets are being generated for transmission 4. Both the ASYNC request and response queues are empty 2000 Dec 01 NAME AND FUNCTION NAME AND FUNCTION 0.3 V power supply 7 Preliminary specification PDI1394L41 ...
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... The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 2000 Dec 01 CONDITIONS CONDITIONS 1, 2 CONDITIONS CONDITIONS 8 Preliminary specification PDI1394L41 LIMITS UNIT UNIT MIN. MAX. 3.0 3 ...
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... AVxFSYNC is time stamped and placed in the SYT field of the CIP header. The default delay value for the frame sync is 3 bus cycle times (duration of 125 s each) in the future, and is transmitted on the very next isochronous cycle regardless of available data. The PDI1394L41 allows this value to be programmable from cycle times (see Section 13.2.1). Additionally, for some audio applications, the SYT value can be programmed to be appended only to isochronous cycles that have application data attached to them ...
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... The attached device is prepared to receive a byte. The L41 will not assert AVxVALID for any cycle in which AVxREADY is false. When the AV port is configured as a receiver, the AVxSYNC signal will be asserted as soon as the PDI1394L41 AVx port has an application packet available for delivery (independent of AVxREADY) and will remain asserted until the first byte of the application packet is clocked from the AV port ...
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... Figure 1. Behavior of “SY” signal at AVport of receiver 12.2.7 Programmable Buffer Memory The PDI1394L41 maintains six distinct buffers that are highly configurable to optimize bandwidth capabilities. Buffers can be increased or decreased from the default value by accessing the indirect address range of 0x100 through 0x1FC (INDADDR, 0x0F8). If the AV Layer is configured to transmit or receive DVB compliant MPEG-2 type data, the default Isochronous (AV) buffer sizes are recommended. FIFO sizes cannot be changed dynamically ...
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... Bushold and Link/PHY single capacitor galvanic isolation 12.3.1 Bushold The PDI1394L41 uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by a 3-Stated device or input coupling capacitor. Unterminated high impedance inputs react to ambient electrical noise which cause internal oscillation and excess power supply current draw. The following pins have bushold circuitry enabled when the ISON pin is in the logic “ ...
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... FOR MORE DETAILS 12.4 Power Management The PDI1394L41 implements several features for power management as noted in the 1394a–2000 standard. These features include: 1. Reset of the Phy/Link interface by setting the RPL bit in the LNKCTL register. 2. Disable of the Phy/Link interface caused by either setting the SWPD bit in the RDI register –OR– asserting (high) the PD pin. ...
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... It is possible to read/modify/write a register using the shadow register (0x0F4) without rewriting all 4 bytes. For example, to modify an enable bit in the fourth byte of the Asynchronous Interrupt Enable (0x0A4), a read of location 0x100+0x0A0+3=0x1A3, followed by a write of the modified byte to the same location 0x100+0x0A0+3=0x1A3 is sufficient. The other bytes remain unchanged. 2000 Dec 01 MUX Preliminary specification PDI1394L41 REGISTERS 32 SV01034 ...
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... Asynchronous Interrupt Enable (0x0A4), a read of location 0x100+0x0A0+3=0x1A3, followed by a write of the modified byte to the same location 0x100+0x0A0+3=0x1A3 is sufficient. The other bytes remain unchanged. 2000 Dec 01 MUX 32 15 Preliminary specification PDI1394L41 REGISTERS 32 SV01035 ...
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... If these bits are set = 0, the corresponding PLI, LOA, SCA, and SCI bit is in the interrupt/status mode as described above. (Also see the individual bit descriptions in the RDI register section of this data sheet... Section 13.3.1) 2000 Dec 01 16 Preliminary specification PDI1394L41 ...
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... Bytes are swapped within the word X 1 16-bit data bus, address as in PDI1394L21 X 0 8-bit data bus, address as in PDI1394L21 Outside Address (A1, A0 BYTE 1 BYTE 2 BYTE 3 17 Preliminary specification PDI1394L41 Result HIF16 = 1 Inside Address (A1, A0 SV00656 ...
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... With the current host interface such a read is in fact a move operation of the data quadlet from the queue to the shadow register. Once the data is copied into the shadow register longer available in the queue itself so the CPU should always read all 4 bytes, or both words, before attempting any other read access (be careful with interrupt handlers for the PDI1394L41!). 2000 Dec 01 ...
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... In both multiplexed and non-multiplexed mode, HIF WAIT can be used to signal to the controlling CPU that an extension of the current access cycle is needed. This allows the PDI1394L41 to work in the same address space as peripherals with a shorter access time. HIF WAIT will remain HIGH for the minimum duration of the access cycle. If HIF A[8] is HIGH, HIF WAIT will extend the access cycle to 120ns to allow for the shadow register transfer to take place ...
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... Philips Semiconductors 1394 content protection AV link layer controller HIF CS_N HIF RD_N HIF WR_N HIFA7–A0 HIFD15–D8 HIFAD7–AD0 A8 HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. ALE line is held LOW. 2000 Dec 01 Figure 7. 16 Bit Write Cycle Non-multiplexed 20 Preliminary specification PDI1394L41 SV01867 ...
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... AD7–AD0 A7–A0 HIFD15–D8 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. Second write cycle elongated by WAIT signal. 2000 Dec 01 t ALEH t PWALE ADDR DATA ADDR LATCHED DATA Figure 8. 16 Bit Write Cycle Multiplexed 21 Preliminary specification PDI1394L41 DATA LATCHED DATA SV01854 ...
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... HIF CS_N t ALES HIF ALE HIF AD7–AD0 HIF A7–A0 HIFD15–D8 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT 2000 Dec 01 t ALEH t PWALE ADDR DA TA ADDR LATCHED DATA Figure 9. 16 Bit Read Cycle Multiplexed 22 Preliminary specification PDI1394L41 DA TA LATCHED DATA SV01855 ...
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... AV link layer controller HIF CS_N t ALES HIF ALE AD7–AD0 A7–A0 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT 2000 Dec 01 t ALEH t PWALE ADDR DATA ADDR LATCHED Figure 10. 8 Bit Write Cycle Multiplexed 23 Preliminary specification PDI1394L41 DATA LATCHED SV01856 ...
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... AV link layer controller HIF CS_N t ALES HIF ALE HIF AD7–AD0 HIF A7–A0 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT 2000 Dec 01 t ALEH t PWALE ADDR DA TA ADDR LATCHED Figure 11. 8 Bit Read Cycle Multiplexed 24 Preliminary specification PDI1394L41 DA TA LATCHED SV01857 ...
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... Philips Semiconductors 1394 content protection AV link layer controller HIF CS_N HIF RD_N HIF WR_N HIFA7–A0 HIFAD7–AD0 A8 HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. ALE line is held LOW. 2000 Dec 01 Figure 12. 8 Bit Write Cycle Non-multiplexed 25 Preliminary specification PDI1394L41 SV01866 ...
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... Philips Semiconductors 1394 content protection AV link layer controller HIF CS_N HIF RD_N HIF WR_N HIF A8 HIFA7–A0 HIFAD7–AD0 HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. ALE line is held LOW. 2000 Dec 01 Figure 13. 8 Bit Read Cycle Non-multiplexed 26 Preliminary specification PDI1394L41 SV01865 ...
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... Philips Semiconductors 1394 content protection AV link layer controller 12.6 The Asynchronous Packet Interface The PDI1394L41 provides an interface to asynchronous data packets through the registers in the host interface. The format of the asynchronous packets is specified in the following sections. 12.6.1 Reading an Asynchronous Packet Upon reception of a packet, the packet data is stored in the appropriate receive FIFO, either the Request or Response FIFO. The location of the packet is indicated by either the RREQQQAV or RRSPQAV status bit being set in the Asynchronous Interrupt Acknowledge (ASYINTACK) register ...
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... If the dataLength mod 4 is not zero, then zero-value bytes are added onto the end of the packet to guarantee that a whole number of quadlets is sent. 2000 Dec 01 Description 28 Preliminary specification PDI1394L41 ...
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... Figure 15. Quadlet/Block Write Response Packet Transmit Format 2000 Dec 01 0 spd tLabel rt tCode destinationID destinationOffsetHigh destinationOffsetLow 0 spd tLabel rt tCode destinationID rCode 29 Preliminary specification PDI1394L41 priority SV01080 priority SV01081 ...
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... Figure 17. Quadlet Read Response Transmit Format 2000 Dec 01 0 spd tLabel rt tCode destinationID destinationOffsetHigh destinationOffsetLow quadlet data 0 spd tLabel rt tCode destinationID rCode quadlet data 30 Preliminary specification PDI1394L41 priority SV01082 priority SV01083 ...
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... AV link layer controller Figure 18. Block Read Request Transmit Format 2000 Dec 01 0 spd tLabel rt tCode destinationID destinationOffsetHigh destinationOffsetLow data length 31 Preliminary specification PDI1394L41 priority SV01084 ...
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... Figure 20. Block Read or Lock Response Transmit Format 2000 Dec 01 0 spd tLabel rt tCode destinationID destinationOffsetHigh destinationOffsetLow dataLength extendedTcode Block data padding (if needed) Figure 19. Block Packet Transmit Format 0 spd tLabel rt tCode destinationID rCode dataLength extendedTcode Block data padding (if needed) 32 Preliminary specification PDI1394L41 priority SV01085 priority SV01086 ...
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... Asynchronous Stream Transmit The PDI1394L41 supports asynchronous stream as specified in IEEE1394.a. The asynchronous stream packet format is shown below. The first quadlet contains packet control information. The second quadlet contains datalength, tag, channel number, and synchronization code. The third quadlet contains the datalength in quadlets ...
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... Block write requests Block read responses Lock requests Lock responses Concatenated self-ID / PHY packets Confirmation of packet transmission Description Reserved. packet OK. Reserved. Data CRC error and/or block size mismatch have been detected. Reserved. 34 Preliminary specification PDI1394L41 TRANSACTION CODE hex E hex ...
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... This revision of the AV Link will not generate other acknowledge codes, but may receive them from 0111 – 1100, newer (1394 A) links. In that case, these new values will show up here. and 1111 2000 Dec 01 Description 35 Preliminary specification PDI1394L41 ...
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... Dec 01 destinationID tLabel rt tCode sourceID destinationOffsetHigh destinationOffsetLow spd destinationID tLabel rt tCode sourceID rCode spd Figure 24. Write Response Receive Format 36 Preliminary specification PDI1394L41 priority ackSent SV00257 priority u ackSent SV00258 ...
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... Figure 26. Quadlet Read Response Receive Format 2000 Dec 01 destinationID tLabel rt tCode sourceID destinationOffsetHigh destinationOffsetLow quadlet data spd destinationID tLabel rt tCode sourceID rCode quadlet data spd 37 Preliminary specification PDI1394L41 priority ackSent SV00259 priority u ackSent SV00260 ...
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... AV link layer controller 2000 Dec 01 destinationID tLabel rt tCode sourceID destinationOffsetHigh destinationOffsetLow data length spd Figure 27. Block Read Request Receive Format 38 Preliminary specification PDI1394L41 priority ackSent SV00261 ...
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... Figure 29. Block Read or Lock Response Receive Format 2000 Dec 01 destinationID tLabel rt tCode sourceID destinationOffsetHigh destinationOffsetLow dataLength extendedTcode Block data padding (if needed) spd destinationID tLabel rt tCode sourceID rCode dataLength extendedTcode Block data padding (if needed) spd 39 Preliminary specification PDI1394L41 priority ackSent SV00262 priority u ackSent SV00263 ...
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... Dec 01 dataLength tag chanNum 1010 Block data (possibly zero) spd 1110 self ID packet data 00 Figure 30. Self-ID Receive Format 1110 PHY packet first quadlet Figure 31. PHY Packet Receive Format 40 Preliminary specification PDI1394L41 sy 2 status SV01052 0000 2 2 ackSent SV00264 0000 2 2 SV00265 ...
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... Interrupts The PDI1394L41 provides a single interrupt line (HIF INTN) for connection to a host controller. Status indications from five major areas of the device are collected and ORed together to activate HIF INTN. Status from four major areas of the device are collected in five status registers; ...
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... IRXINTACK (0x04C ITXINTACK (0x02C Figure 33. Interrupt Hierarchy 42 Preliminary specification PDI1394L41 LNKPHYINTACK (0x008) ASYINTACK (0x0A0) SV01858 ...
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... DBS FN QPC FDF Preliminary specification PDI1394L41 VERSION CODE ATACK ...
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... Dec TAG CHANNEL DBS FN QPC FDF SPD TAG CHANNEL Preliminary specification PDI1394L41 SPD EMI BPAD SYT ...
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... LAST QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE (WRITE ONLY) QUADLET OF PACKET FROM RECEIVER REQUEST QUEUE (TRANSFER REGISTER) QUADLET OF PACKET FROM RECEIVER RESPONSE QUEUE (TRANSFER REGISTER Preliminary specification PDI1394L41 TOF ...
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... INDADDR 0x0F8 INDDATA 0x0FC 2000 Dec byte 1 byte RESERVED WINDOW TO THE INDIRECT QUADLET POINTED TO BY INDADDR 46 Preliminary specification PDI1394L41 byte INDADDR SV01033 ...
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... BSYCTRL Reset Value 0x46000002 Bit 31: R/W IDValid (IDVALID): When equal to one, the PDI1394L41 accepts the packets addressed to this node. This bit is automatically set after selfID complete and node ID is updated. Bit 30: R/W Receive Self ID (RCVSELFID): When asserted, the self-identification packets, generated by each PHY device on the bus, during bus initialization are received and placed into the asynchronous request queue as a single packet ...
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... Bit 11: R/W Cycle Master (CYMASTER): When asserted and the PDI1394L41 is attached to the root PHY (ROOT bit = 1), and the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle Master function in such a case, first reset CYMASTER, then set it again ...
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... Cycle Pending (CYPEND): Cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and stays asserted until the isochronous cycle has ended. Bit 0: R/W Cycle Lost (CYLOST): The cycle timer has rolled over twice without the reception of a cycle start packet. This only occurs when cycle master is not asserted. 2000 Dec 01 SV01040 49 Preliminary specification PDI1394L41 ...
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... CYCLE_SECONDS Reset Value 0x00000000 Bit 31..25: R/W Seconds count: 1-Hz cycle timer counter. Bit 24..12: R/W Cycle Number: 8kHz cycle timer counter. Bit 11..0: R/W Cycle Offset: 24.576MHz cycle timer counter. 2000 Dec 01 SV00894 CYCLE_NUMBER CYCLE_OFFSET SV00276 50 Preliminary specification PDI1394L41 ...
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... PHYRGAD Reset Value 0x00000000 Bit 31: R/W Read Phy Chip Register (RDPHY): When asserted, the PDI1394L41 sends a read register request with address equal to Phy the Phy interface. This bit is cleared when the request is sent. Bit 30: R/W Write Phy Chip Register (WRPHY): When asserted, the PDI1394L41 sends a write register request with address equal to Phy the Phy interface ...
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... TMBRE is set (1), the TMGOSTOP bit function is disabled; the TMCONT bit function is still available. NOTE: When TMCONT = 1, failing to acknowledge a TIMER interrupt has no effect on the starting/restarting of the timer interrupt is not acknowledged (bit reset), the timer will continue to time out and restart. 2000 Dec 01 PRELOAD SV01096 52 Preliminary specification PDI1394L41 ...
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... HIGH for at least the duration of one AVxCLK period. Failure may cause the application interface of this module to be improperly reset (or not reset at all). When reset is enabled, all bytes will be flushed from the FIFO and transmission will cease immediately. 2000 Dec 01 TRDEL MAXBL PM 53 Preliminary specification PDI1394L41 SV01862 ...
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... AVFSYNCIN has been detected or all ‘1’ such edge was detected since the previous packet. The upper 8 bits of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status Register is unset (=0), the full 24 bits can be set to any application specified value. 2000 Dec 01 DBS FN QPC SV01747 FN . FDF SYT SV00281 54 Preliminary specification PDI1394L41 ...
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... These are the enabled bits for the AV Transmitter Control Reset Value 0x00000000 Bits 13..0 are interrupt enable bits for the Isochronous Transmitter Interrupt Acknowledge register (ITXINTACK). 2000 Dec 01 SV01054 SV01055 55 Preliminary specification PDI1394L41 ...
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... ITXMF: memory is completely full, no storage available. Bit 2: R ITXMAF: almost full, exactly one quadlet of storage available. Bit 1: R ITXM5AV: at least 5 more quadlets of storage available. Bit 0: R ITXME: memory bank is empty (zero quadlets stored). 2000 Dec 01 SPD EMI TAG CHANNEL SV01016 SV01056 56 Preliminary specification PDI1394L41 ...
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... AVCLK and ensure that the reset bit is kept (programmed) HIGH for at least the duration of one AVCLK period. Failure may cause the application interface of this module to be improperly reset (or not reset at all). 2000 Dec 01 BPAD SV00887 57 Preliminary specification PDI1394L41 ...
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... E1: End of Header, F1: Format: Should be set to 10 for second AV header quadlet. Bit 29..24: R FMT: Value inserted in the Format field. Bit 23..0: R FDF/SYT: If ‘‘EN FS” in Register IRXPKCTL (0x040) is set to ‘1’, then lower 16-bits are interpreted as SYT. 2000 Dec 01 DBS FN QPC FMT FDF SYT 58 Preliminary specification PDI1394L41 SV00286 SV00287 ...
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... Interrupt enable bits for AV Receiver Reset Value 0x00000000 Bit 13..0 are interrupt enable bits for the Isochronous Receiver Interrupt Acknowledge (IRXINTACK). 2000 Dec 01 SV01025 SV01026 59 Preliminary specification PDI1394L41 ...
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... Dec 01 SPD TAG CHANNEL ERR SV01041 60 Preliminary specification PDI1394L41 ...
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... IRXM512LFT: FIFO is 512 quadlets from full. Bit 3: R IRXMF: Full: no space available. Bit 2: R IRXMAF: Almost full: exactly one quadlet of storage available. Bit 1: R IRXM5AV: At least 5 more quadlets of storage available. Bit 0: R RXME: Memory bank is empty (no data committed). 2000 Dec 01 SV01057 61 Preliminary specification PDI1394L41 ...
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... TREQQF: Transmitter request queue full. Bit 2: R TREQQAF: Transmitter request queue almost full (precisely 1 more quadlet available). Bit 1: R TREQQ5AV: Transmitter request queue at least 5 quadlets available. Bit 0: R TREQQE: Transmitter request queue empty. 2000 Dec 01 MAXRC TOS TOF SV00889 SV00918 62 Preliminary specification PDI1394L41 ...
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... Bit 31..0: W TX_RP_LAST: Last quadlet of packet for transmitter response queue (write only). Writing this register will clear the TRSPQWR flag until the quadlet has been written to its queue. 2000 Dec 01 TX_RQ_NEXT SV00293 TX_RQ_LAST SV00294 TX_RP_NEXT SV00295 TX_RP_LAST SV00296 63 Preliminary specification PDI1394L41 ...
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... TRSPQWR: Transmitter response queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt. Bit 0: R/W TREQQWR: Transmitter request queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt. 2000 Dec 01 RREQ RRSP Preliminary specification PDI1394L41 SV00297 SV00298 ...
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... ESCA: Enable SCLK active interrupt. Leaving this bit in the reset (0) state allows the SCA bit to be read as a status bit. Bit 16: R/W ESCI: Enable SCLK inactive interrupt. Leaving this bit in the reset (0) state allows the SCI bit to be read as a status bit. 2000 Dec Preliminary specification PDI1394L41 SV00797 8 ...
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... A8 not asserted will be directed to the shadow register. To verify the settings of LTLEND and DATAINV, this register is initialized to 0x0F0A0500 on power up. Note, unlike the other registers in this device, access to this register should not be addressed with address line 2000 Dec BYTE 1 BYTE 2 66 Preliminary specification PDI1394L41 BYTE 3 SV01817 ...
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... These extensions have been implemented via an indirect addressing mechanism. This mechanism allows software written for previous versions of the AV Link (PDI1394L21 and PDI1394L11) to operate on the PDI1394L41 with minimal changes. To read or write from the indirect memory, you first write the appropriate address into the indirect address register (A8 = 1), then read or write from (or to) the indirect data increment the indirect address by one quadlet ...
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... RRSP 000011 000100 RREQ 000111 001000 TRSP 001011 001100 TRSP 001111 & 111111 010000 IRX 011111 100000 & 000000 ITX 101111 fifo_bank SV01765 base_fifo end_fifo Preliminary specification PDI1394L41 SV01766 ...
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... Preliminary specification PDI1394L41 SV01767 SV01768 SV01769 ...
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... Unused bits read ‘0’ Bit 5..0 R/W end_fifo: End address of the FIFO 2000 Dec end_fifo base_fifo end_fifo base_fifo Preliminary specification PDI1394L41 SV01770 SV01771 ...
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... Output Output Input/Output CYCLEOUT HIF INTN PHY D[0:7] CLK50 PHY CTL[0:1] HIF WAIT AVxEMI AV1ERR0 AV1ERR1 71 Preliminary specification PDI1394L41 UNIT NOTE V Pin categories Pin categories Pin categories LOW to HIGH transition Pin categories HIGH to LOW transition Pin category 9 V ...
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... Figure 40 Figure 40 Figure 40 Figure 40 Figure 40 Figure 40 Figure 40 Figure 40 Figure 41 Figure 41 Figure 41 Figure 42 Figure 43 Figures 8, 9, 10, 11 Figures 8, 9, 10, 11 Figures 8, 9, 10, 11 – – 72 Preliminary specification PDI1394L41 LIMITS +70 C UNIT amb MIN TYP MAX 41. ...
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... MESSAGE ASSERTED IN THE EVENT OF A BUS PACKET CRC ERROR t t WHIGH WLOW É É É t PERIOD É É É VALID t OD Figure 36. AV Interface Timing Diagram t PWFS Figure 37. AVxFSYNC Timing Diagram 73 Preliminary specification PDI1394L41 INVALID DATA MESSAGE SV00240 SV01864 SV00890 ...
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... PHY D[0:7], PHY CTL[0:1] Figure 38. PHY D[0:7], PHY CTL[0:1] Input Setup and Hold Timing Waveforms PHY D[0:7], PHY CTL[0:1], LREQ Figure 39. PHY D[0:7], PHY CTL[0:1], and LREQ Output-Delay Timing Waveforms 2000 Dec 01 t SCLKPER 50% t SUP t HP 50% 50% SCLK 50 50% SV00694 74 Preliminary specification PDI1394L41 50% SV00919 ...
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... ACC t PWWAIT t WRP VALID Figure 40. Host Interface Timing Waveforms 75 Preliminary specification PDI1394L41 VALID SV01869 ...
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... AV link layer controller 16.5 CYCLEIN/CYCLEOUT Timings CYCLEIN SCLK CYCLEIN CYCLEOUT 16.6 RESET Timings RESET_N 2000 Dec 01 50% 50% 50 CWH CWL t CP Figure 41. CYCLEIN Waveform 50 50% Figure 42. CYCLEOUT Waveforms 50% 50% t RESET SV00698 Figure 43. RESET_N Waveform 76 Preliminary specification PDI1394L41 SV00696 50 50% SV00697 ...
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... Philips Semiconductors 1394 content protection AV link layer controller LQFP144: plastic low profile quad flat package; 144 leads; body 1.4 mm 2000 Dec 01 77 Preliminary specification PDI1394L41 SOT486-1 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2000 Dec 01 [1] Copyright Philips Electronics North America Corporation 2001 Document order number: 78 Preliminary specification PDI1394L41 All rights reserved. Printed in U.S.A. Date of release: 01-01 9397 750 07931 ...
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... SCLK input of the L41 make the pin go to the LOW state when the clock is not present. The value of the resistor is R= 3.3 KOhms; a 1/10th watt type is sufficient. Errata To the PDI1394L41 1394 AV Link Layer Controller (Data Sheet dated: 2000 December 01). ERRATA FOR THE PHILIPS Philips Semiconductors December 01, 2000 – ...
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... See the Restricted Errata document for this errata... it deals with a DTCP regulated aspect of the L41. E–6 See the Restricted Errata document for this errata... it deals with a DTCP regulated aspect of the L41. Errata To the PDI1394L41 1394 AV Link Layer Controller (Data Sheet dated: 2000 December 01). Philips Semiconductors December 01, 2000 – Page 80 ...