pdi1394l41 NXP Semiconductors, pdi1394l41 Datasheet - Page 76
pdi1394l41
Manufacturer Part Number
pdi1394l41
Description
1394 Content Protection Av Link Layer Controller
Manufacturer
NXP Semiconductors
Datasheet
1.PDI1394L41.pdf
(83 pages)
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1. Timing shown is for AVxFSYNC used as an output only. When AVxFSYNC is used as an input, only the rising edge of the signal is
Philips Semiconductors
16.0 TIMING DIAGRAMS
16.1 AV Interface Operation
16.2 AV Interface Critical Timings
NOTE:
2000 Dec 01
1394 content protection AV link layer controller
considered as long as the input pulse width exceeds 40 nS.
AVSYNC, AVENDPCK
AV D [7:0], AVVALID,
AV D[7:0]
AVERR[0]
AVERR[1]
AVSYNC
AVVALID
AVCLK
AV D [7:0], AVERR[1:0],
SY, READY
AVSYNC, AVVALID
É É É
É É É
AVCLK
AVxFSYNC
MESSAGE
t
SU
Figure 35. AV Parallel Interface Operation Diagram
ASSERTED IN THE EVENT OF A DATA BLOCK SEQUENCE ERROR
VALID
ASSERTED IN THE EVENT OF A BUS PACKET CRC ERROR
Figure 36. AV Interface Timing Diagram
Figure 37. AVxFSYNC Timing Diagram
t
IH
INVALID DATA
É É É
É É É
t
WHIGH
t
OD
t
PWFS
73
t
PERIOD
MESSAGE
VALID
t
WLOW
INVALID DATA
SV00890
MESSAGE
PDI1394L41
SV01864
Preliminary specification
SV00240
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