pdi1394p25 NXP Semiconductors, pdi1394p25 Datasheet
pdi1394p25
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pdi1394p25 Summary of contents
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... PDI1394P25 1-port 400 Mbps physical layer interface Preliminary data Supersedes data of 2001 Jul 18 hilips Semiconductors INTEGRATED CIRCUITS 2001 Sep 06 ...
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... The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PDI1394P25 is designed to interface with a Link Layer Controller (LLC), such as the PDI1394L40 or PDI1394L41. ORDER CODE ...
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... PD 15 LPS 2001 Sep PDI1394P25 Preliminary data PDI1394P25 AGND AGND 38 TPBIAS0 37 TPA0+ 36 TPA0– 35 TPB0+ 34 TPB0– ...
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... E8 ISO PLLV PLLGND F3 CNA PLLV BRIDGE F6 C/LKON TESTM F7 PC0 DV F8 PC2 DD 4 Preliminary data PDI1394P25 SV01909 Signal Ball Signal G1 DGND G2 DGND G3 CTL0 G4 CTL1 DGND G8 DGND H1 LREQ H2 SYSCLK LPS ...
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... Cable Power Status input. This terminal is normally connected to cable power through a 390 k resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. G3 I/O Control I/Os. These bi-directional signals control communication G4 between the PDI1394P25 and the LLC. Bus holders are built into these terminals. 5 Preliminary data PDI1394P25 Description , bit ...
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... The LPS input must be high for at least order to be guaranteed to be observed as high by the PHY. When the PDI1394P25 detects that LPS is inactive, it will place the PHY-LLC interface into a low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored ...
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... LLC Test control input. This input is used in manufacturing tests of the PDI1394P25. For normal use, this terminal should be tied to GND Test control input. This input is used in manufacturing tests of the PDI1394P25. For normal use, this input may be tied to V compatibility with other vendors’ ...
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... TESTM PD /RESET 7.0 FUNCTIONAL SPECIFICATION The PDI1394P25 requires only an external 24.576 MHz crystal as a reference. An external clock can be connected to XI instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded Strobe and Data information ...
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... The TEST0 terminal is used to set up various manufacturing test conditions. For normal operation, it should be connected to ground. The TESTM terminal is used in manufacturing tests of the PDI1394P25. For normal use, it may be tied to either PHY V compatability with other vendors’ pin-compatible PHY chips PHY GND (when a PDI1394P25 is an alternate device). ...
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... Mbps physical layer interface The LPS input is considered inactive if it remains low for more than 2.6 s and is considered active otherwise. When the PDI1394P25 detects that LPS is inactive, it will place the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored ...
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... Between TPA and TPB cable inputs, S100 operation Between TPA and TPB cable inputs, S200 operation Between TPA and TPB cable inputs, S400 operation Crystal connected according to Figure 10 or external clock input at pin XI 11 Preliminary data PDI1394P25 MIN MIN TYP TYP MAX MAX ...
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... Drivers disabled Drivers disabled Drivers disabled Drivers disabled TPBIAS–TPA common mode voltage, drivers disabled 200 Mbps TPBIAS–TPA common mode voltage, drivers disabled 400 Mbps Drivers disabled 12 Preliminary data PDI1394P25 LIMITS UNIT UNIT MIN TYP MAX 172 — 265 mV –0.88 — ...
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... 1 ISO = 0 V ISO = 0. LREF 0. LREF DD At rated I current Preliminary data PDI1394P25 MIN TYP MAX UNIT — 56 — mA — 40 — mA — 38 — mA — 150 — A 4.7 — 7.5 V 2.4 — — ...
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... At 1394 connector 90% to 10%; At 1394 connector 50% to 50%; See Figure 2 50% to 50%; See Figure 2 50% to 50%; See Figure 3 SYSCLK Dn, CTLn Figure 3. Dn, CTLn, output delay relative to SYSCLK SV01099 14 Preliminary data PDI1394P25 LIMITS UNIT UNIT MIN TYP MAX — 68 — C/W MIN ...
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... Extended register definition. For the PDI1394P25, this field is 111b, indicating that the extended register set is implemented. Num_Ports 4 Rd Number of ports. This field indicates the number of ports implemented in the PHY. For the PDI1394P25 this field is 1. PHY_Speed 3 Rd PHY speed capability. For the PDI1394P25, this field is 010b, indicating S400 speed capability. ...
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... Port_Select. This field selects the port when accessing per-port status or control (e.g., when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset hardware reset and is unaffected by bus reset. The only valid number for the PDI1394P25 is 0. 2001 Sep 06 DESCRIPTION 20 ns ...
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... Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the selected port, encoded as follows: The Peer_Speed field is invalid after a bus reset until self-ID has completed. NOTE: Peer speed codes higher than 010b (S400) are defined in P1394a. However, the PDI1394P25 is only capable of detecting peer speeds up to S400. PIE ...
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... Product identifier. For the PDI1394P25, this field is 41_28_01 (the MSB is at register address 1101b). The Vendor-Dependent page provides access to the special control features of the PDI1394P25, as well as configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page Select field in base register 7. The configuration of the Vendor-Dependent page is shown in Table 7 and corresponding field descriptions given in Table 8 ...
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... LLC in combination). However, this field does not affect the PHY speed capability indicated to peer PHYs during self-ID; the PDI1394P25 PHY identifies itself as S400 capable to its peers regardless of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset. ...
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... OUTER SHIELD TERMINATION OUTER CABLE SHIELD 0.1 F LINK POWER SQUARE WAVE INPUT ( SV01805 Figure 7. Non-isolated connection variations for LPS 20 Preliminary data PDI1394P25 OUTER SHIELD TERMINATION SV01830 NON-ISOLATED OUTER CABLE SHIELD CHASSIS GROUND SV01748 10 k LPS LPS 10 k SV01806 ...
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... Sep 06 DD LINK LAYER CHIP LPS CONTENDER/ LINKON SV01807 LINK LAYER CHIP LINKON Figure 9. Three configurations for C/LKON signal Preliminary data PDI1394P25 PHY CHIP 10 K C/LKON 10 K TIE TO LLCV (CONTENDER GND (NOT CONTENDER) PHY CHIP C/LKON SV01873 non-isolated system ...
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... OR THROUGH OPTOCOUPLER FOR GALVANIC ISOLATION. USE 0.1 F CAPACITOR TO GND ONLY IN NON-LINK DESIGNS. 0.001 PDI1394P25 390 k Figure 10. External Component Connections 22 Preliminary data PDI1394P25 48 AGND ...
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... Using the PDI1394P25 with a lower-speed link layer Although the PDI1394P25 is an S400 capable PHY, it may be used with lower speed LLCs. In such a case, the LLC has fewer data terminals than the PHY, and some Dn terminals on the PDI1394P25 will be unused. Unused Dn terminals should be pulled to ground through 10 k resistors ...
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... However, as explained below, the speed reported in the self-ID packet of a PDI1394P25 PHY may be adjusted to account for a slow link chip. In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the node (lesser of the PHY and LLC speed) is that of the lower-speed LLC ...
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... Typically, changes should be done to both load capacitors (C9 and C10 above) at the same time, and both should be of the same value. Additional design details and requirements may be provided by the crystal vendor. SV01809 25 Preliminary data PDI1394P25 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 18.0 PRINCIPLES OF OPERATION The PDI1394P25 is designed to operate with an LLC such as the Philips Semiconductors PDI1394L11 or PDI1394L21. The following paragraphs describe the operation of the PHY-LLC interface. The interface to the LLC consists of the SYSCLK, CTL0–CTL1, D0–D7, LREQ, LPS, C/LKON, and ISO terminals on the PDI1394P25 as shown in Figure 13 ...
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... All others NOTE: The PDI1394P25 will accept a bus request with an invalid speed code and process the bus request normally. However, during packet transmission for such a request, the PDI1394P25 will ignore any data presented by the LLC and will transmit a null packet. ...
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... The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the PDI1394P25 during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start packet is imminent, and then re-enables the enhancements when it receives a cycle start packet ...
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... Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines bus reset is pending, the PHY may also assert Grant on the CTL line immediately following a complete status transfer. DESCRIPTION ( S[0:1] S[14:15] Figure 15. Status Transfer Timing 29 Preliminary data PDI1394P25 ( SV01759 ...
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... FF (“data-on”) NOTE: SPD = Speed code; see Table 19; d0–dn = Packet data. 2001 Sep 06 PDI1394P25 sends at least one “data-on” indication before sending the speed code or terminating the receive operation. The PDI1394P25 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization to the LLC. This packet is transferred to the LLC just as any other received self-ID packet ...
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... D lines for one or more cycles. Receive operation terminated. The PHY terminates the receive operation by asserting Idle on the CTL lines. The PHY shall assert at least one cycle of Idle following a receive operation. (a) 10 (b) FF (“data-on”) Figure 17. Null Packet Reception Timing 31 Preliminary data PDI1394P25 00 (c) 00 SV01761 ...
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... Link Controls Ctl and D PHY High-impedance Ctl and D Outputs Figure 18. Normal Packet Transmission Timing 32 Preliminary data PDI1394P25 ( SPD ...
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... PHY and LLC (whether of the Philips bus-holder type or Annex J type) the LPS signal must be pulsed direct connection, the LPS signal may be either a pulsed or a level signal. Timing parameters for the LPS signal are given in Table 20. 33 Preliminary data PDI1394P25 (d) ( ...
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... CLK_ACTIVATE NOTES: 1. The specified T and T times are worst–case values appropriate for operation with the PDI1394P25. These values are broader than LPSL LPSH those specified for the same parameters in the P1394a Supplement (i.e., an implementation of LPS that meets the requirements of P1394a will operate correctly with the PDI1394P25). ...
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... When LPS is asserted, the interface will be initialized as described on the next page. (c) (a) (b) T LPS_RESET Figure 21. Interface Reset, ISO High 35 Preliminary data PDI1394P25 time, the PHY determines that LPS_RESET time, the LLC RESTORE interval RESTORE (d) T RESTORE SV01811 ...
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... PHY. The timing for interface disable is shown in Figure 22 and Figure 23. When the interface is disabled, the PHY will enter a low-power state if none of its ports is active. (a) (c) (b) T LPS_RESET T LPS_DISABLE Figure 22. Interface Disable, ISO Low 36 Preliminary data PDI1394P25 time, the LLC RESTORE interval RESTORE . When LPS_DISABLE (d) SV01812 ...
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... LPS_DISABLE placing the SYSCLK output into a high-impedance state. The PHY-LLC interface is now in the disabled state. (c) (a) (b) T LPS_RESET T LPS_DISABLE Figure 23. Interface Disable, ISO High 37 Preliminary data PDI1394P25 time, the PHY determines that LPS_RESET time, the PHY terminates SYSCLK activity by (d) SV01813 ...
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... After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal operation when LPS is reasserted by the LLC. The timing for interface initialization is shown in Figure 24 and Figure 25. 7 cycles (c) 5 ns. min 10 ns. max (b) Figure 24. Interface Initialization, ISO Low 38 Preliminary data PDI1394P25 (d) SV01814 ...
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... Initialization complete. The PHY asserts the Idle state on the CTL lines and logic 0 on the D lines. This indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The PHY will now accept requests from the LLC via the LREQ line. 39 Preliminary data PDI1394P25 SV01815 ...
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... Node is powered from the bus and uses additional power is needed to enable the link. 110 Node is powered from the bus and uses additional needed to enable the link. 111 Node is powered from the bus and uses additional needed to enable the link. 2001 Sep 06 DESCRIPTION 40 Preliminary data PDI1394P25 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm 2001 Sep 06 41 Preliminary data PDI1394P25 SOT314-2 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface LFBGA64: plastic low profile fine-pitch ball grid array package; 64 balls; body 1.05 mm 2001 Sep 06 42 Preliminary data PDI1394P25 SOT534-1 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 2001 Sep 06 NOTES 43 Preliminary data PDI1394P25 ...
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... Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. hilips Semiconductors 2001 Sep 06 Fax: + 24825 Document order number: 44 Preliminary data PDI1394P25 Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Date of release: 09-01 9397 750 08751 ...