pdi1394p25 NXP Semiconductors, pdi1394p25 Datasheet - Page 38

• Manufacturer Part Number: pdi1394p25
• Description: 1-port 400 Mbps Physical Layer Interface
• Manufacturer: NXP Semiconductors

1. Normal operation. Interface is operating normally, with LPS
2. LPS deasserted. The LLC deasserts the LPS signal and, within
3. Interface reset. After T
Philips Semiconductors
The sequence of events for disabling the PHY-LLC interface when it
is in the non-differentiated mode of operation (ISO terminal is high)
is as follows:
2001 Sep 06
1-port 400 Mbps physical layer interface
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via the
LREQ line.
1.0 ms, terminates any request or interface bus activity, places
its CTL and D outputs into a high-impedance state, and drives its
LREQ output low.
LPS is inactive, terminates any interface bus activity, and drives
SYSCLK
D0 – D7
LREQ
CTL0
CTL1
LPS
ISO
LPS_RESET
(low)
(a)
time, the PHY determines that
T
CLK_ACTIVATE
Figure 24. Interface Initialization, ISO Low
(b)
5 ns. min
10 ns. max
7 cycles
38
4. Interface disabled. If the LPS signal remain inactive for
After the interface has been reset, or reset and then disabled, the
interface is initialized and restored to normal operation when LPS is
reasserted by the LLC. The timing for interface initialization is shown
in Figure 24 and Figure 25.
its CTL and D outputs low. The PHY-LLC interface is now in the
reset state.
T
driving the SYSCLK output low. The PHY-LLC interface is now in
the disabled state.
LPS_DISABLE
(c)
time, the PHY terminates SYSCLK activity by
(d)
PDI1394P25
Preliminary data
SV01814