pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 28

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

PEB 2045
PEF 2045
According to figure 16 in the primary access configuration the connection memory is usually
programmed to switch the system and synchronous interface inputs to the synchronous and system
interface outputs, respectively. However, it is also possible to connect the system interface inputs
to the system interface outputs as well as the synchronous interface inputs to the synchronous
interface outputs. This connection possibility allows for test loops at the system and the
synchronous interfaces.
Figure 16
Connection Choices in the Primary Access Configuration
2.5
Space Switch Mode
The space switch mode is selected by the mode bits MI1, MI0, MO1, MO0 = D
.
H
In the space switch mode the basic operational principles differ from those outlined in chapter 2.1.
In the speech memory only a quarter frame is stored restricting the connection capabilities of the
PEx 2045.
All 16 input lines run at a data rate of 8192 kbit/s delivering 2048 bytes of data in each frame. Since
the speech memory can only hold 512 bytes, the data bytes must be read within a quarter of a frame
period to be outputted on one of the two 8192-kbit/s output lines.
t
In space switch mode it is recommended that the SP pulse be 282
long (N = 70). For proper
CP8
functionality the time-slot numbers of a programmed connection must be equal. In the following only
this case considered.
The output time-slot is encoded in the connection memory address. Since the input time-slot has to
be the same it is not necessary to fully specify it in the CM data. However the 5 least significant bits
must be programmed (see tables 15 and 16).
The speech memory address is composed of 4 bits (D0 through D3) for the coding of the 16 input
(logical line number and pin names match) lines and 5 bits (D4 through D8) for the coding of 32
time-slots. Which of the four blocks of 32 time-slots each is switched to the output lines is
determined by the connection memory address. This consists of 1 bit (IA0) for the marking of one
of two possible output lines with 7 bits (IA1 through IA7) for the 128 time-slots, as shown below.
Semiconductor Group
28