lm2324 National Semiconductor Corporation, lm2324 Datasheet - Page 7

• Manufacturer Part Number: lm2324
• Description: Pllatinum? 2.0 Ghz Frequency Synthesizer For Rf Personal Communications
• Manufacturer: National Semiconductor Corporation

Register
Register
Notes: Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited)
R_CNTR — These bits select the divide ratio of the programmable reference dividers.
2.0 Programming Description
2.1.2 Register Content Truth Table
2.2 R REGISTER
If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into the 14-bit R reg-
ister. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide ratio is programmed using the
bits R_CNTR as shown in table 2.2.1. The ratio must be
larity, charge pump TRI-STATE, and test mode respectively, as shown in 2.2.2. The RS bit is reserved and should always be set
to zero. X denotes a don’t care condition. Data is clocked into the shift register MSB first.
2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter)
2.2.2 R Register Truth Table
If the test mode is NOT activated (R[13]=0), the charge pump is active when CP_TRI is set LOW. When CP_TRI is set HIGH, the
charge pump output and phase comparator are forced to a TRI-STATE condition. This bit must be set HIGH if the test mode is
ACTIVATED (R[13]=1).
If the test mode is NOT activated (R[13]=0), PD_POL sets the VCO characteristics to positive when set HIGH. When PD_POL
is set LOW, the VCO exhibits a negative characteristic where the VCO frequency decreases with increasing control voltage.
If the test mode is ACTIVATED (R[13]=1), the outputs of the N and R counters are directed to the CP
The PD_POL bit selects which counter output according to Table 2.2.3.
2.2.3 Test Mode Truth Table (R[13] = 1)
Divide Ratio
N
R
R
CP_TRI
PD_POL
TEST
1,023
Bit
2
3
•
MSB
N16
R16
17
MSB
R16
X
17
X
R Divider Output
N Divider Output
CP
N15
R15
16
X
R15
o
16
X
Output
N14
R14
15
X
R9
R14
0
0
1
•
15
Location
R[10]
R[11]
R[13]
X
TEST
N13
R13
14
TEST
R13
14
NB_CNTR[9:0]
R8
0
0
1
•
N12
R12
RS
13
R12
RS
13
PD_
POL
N11
R11
12
R7
POL
Charge Pump TRI-STATE
Phase Detector Polarity
Test Mode Bit
PD_
R11
0
0
1
12
•
SHIFT REGISTER BIT LOCATION
N10
CP_
R10
TRI
11
(Continued)
CP_
R10
SHIFT REGISTER BIT LOCATION
TRI
11
Function
N9
R9
10
R6
R_CNTR[9:0]
0
0
1
•
CP_TRI R[10]
2. The PD_POL, CP_TRI and TEST bits control the phase detector po-
Data Field
Data Field
R9
10
N8
R8
9
7
1
1
R8
N7
R7
9
8
R5
0
0
1
•
N6
R6
R7
7
8
N5
R5
NA_CNTR[4:0]
R6
6
7
R4
0
0
1
R_CNTR[9:0]
•
R_CNTR[9:0]
N4
R4
5
R5
Normal Operation
Negative
Normal Operation
6
N3
R3
4
R4
5
R3
0
0
1
•
0
N2
R2
3
R3
4
CTL_WORD[1:0]
o
N1
R1
PD_POL R[11]
R2
R2
2
3
output to allow for testing.
0
0
1
•
R1
2
0
1
N0
R0
1
R0
R1
1
1
1
1
TRI-STATE
Positive
Test Mode
•
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ADDR Field
1
ADDR Field
0
1
0
0
1
R0
0
1
1
LSB
•
LSB