lm2324 National Semiconductor Corporation, lm2324 Datasheet - Page 8

• Manufacturer Part Number: lm2324
• Description: Pllatinum? 2.0 Ghz Frequency Synthesizer For Rf Personal Communications
• Manufacturer: National Semiconductor Corporation

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Register
Notes: Swallow Counter Value: 0 to 31
NB_CNTR
Notes: Divide ratio: 3 to 1,023 (Divide ratios less than 3 are prohibited)
NB_CNTR
2.0 Programming Description
2.3 N REGISTER
If the address bit is LOW (ADDR=0) when LE is transitioned high, data is transferred from the 18-bit shift register into the 17-bit
N register. The N register consists of the 5-bit swallow counter (A counter), the 10-bit programmable counter (B counter) and the
control word. Serial data format is shown below in tables 2.3.1 and 2.3.2. The pulse swallow function which determines the divide
ratio is described in section 2.3.3. Data is clocked into the shift register MSB first.
2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter)
2.3.2 10-Bit Programmable Counter Divide Ratio (B Counter)
2.3.3 Pulse Swallow Function
The N divider counts such that it divides the VCO RF frequency by (P+1) A times, and then divides by P (B - A) times. The B value
(NB_CNTR) must be
as the binary counter value is greater than the swallow counter value (NB_CNTR
f
N = (P x B) + A
f
f
R:
N:
B:
A:
P:
2.3.4 CTL_WORD
Divide Ratio
VCO
VCO
OSC
N
1023
:
:
Swallow Count
= N x (f
3
4
•
Output frequency of external voltage controlled oscillator (VCO)
Output frequency of the external reference frequency oscillator
Preset divide ratio of binary 10-bit programmable reference counter (2 to 1023)
Preset divide ratio of main 15-bit programmable integer N counter (992 to 32,767)
Preset divide ratio of binary 10-bit programmable B counter (3 to 1023)
Preset value of binary 5-bit swallow A counter (0
Preset modulus of dual modulus prescaler (P=32)
MSB
N16
17
NA_CNTR
NA_CNTR
(A)
31
0
1
•
OSC
N15
16
/R)
N16
N14
15
0
0
1
•
3. The continuous divider ratio is from 992 to 32,767. Divider ratios less than 992 are achievable as long
MSB
N13
14
NB_CNTR[9:0]
N15
N12
0
0
1
•
13
CNT_RST
N6
N1
0
0
1
•
N11
12
N14
0
0
1
•
SHIFT REGISTER BIT LOCATION
N10
11
(Continued)
N9
10
NB_CNTR[10:0]
N13
Data Field
0
0
1
•
N5
N8
0
0
1
A
•
9
8
31, A
N7
8
N12
0
0
1
•
N6
7
B)
NA_CNTR[4:0]
N5
NA_CNTR[4:0]
6
N4
0
0
1
N11
•
0
0
1
•
N4
5
PWDN
NA_CNTR).
N0
N3
4
N10
N2
0
0
1
•
3
N3
CTL_WORD[1:0]
0
0
1
•
N1
2
N9
0
1
1
•
LSB
N0
1
N8
1
0
1
•
ADDR Field
N2
0
1
1
•
0
0
N7
LSB
1
0
1
•