at2450 Arrive Technologies, Inc., at2450 Datasheet

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at2450

Manufacturer Part Number
at2450
Description
Deep Channelization Multi-protocol Processor
Manufacturer
Arrive Technologies, Inc.
Datasheet
1.AT2450.pdf (8 pages)
I
Europa is a high-density deep channelization Multi-protocol processor supporting 2048 channels from STS-12c to DS0 with an
aggregate capacity of 1.244Gbps. It allows Ethernet and most data services to be terminated and mapped to/from
SONET/SDH and/or PDH channels. EUROPA provides four individually programmable OC-3/STM-1 or OC-12/STM-4 eight bit
parallel or serial interfaces with SerDes and CDR. It provides a complete ADM or Terminal for PDH or Data services. It supports
deep channelization including any SONET/SDH VCAT payload, 24 DS3/E3s with multi-vendor CSU/DSU subrate and M13/E13
or VT/TU mapped 672/504 DS1, E1, J1s and nxDS0 via an OIF SPI-3 interface. Channelization includes standard-based
contiguous, any random and Virtual Concatenation or PDH VCAT and LCAS in compliance with G.7043. These channels may
include ITU-T I.432.2 (ATM), ITU-T G.7041 (GFP), RFC-1619/1662/2615 (PPP), ITU-T X.85/86 (LAPS), HDLC or BCP mapped
flexibly to SONET or PDH. Encapsulation also includes support for Cisco HDLC, Frame Relay, and Ethernet mapping to either
SONET/SDH or PDH. Additional processing for ML FR, ML PPP, IMA, and L2+ can be provided by an external Access/Network
Processor via the SPI-3 port.
Data is encapsulated then mapped into the SONET/SDH VCAT VCGs, including the 16k-DS0 or 672/504 DS1/E1/J1 or 24
DS3/E3 channels, and then mapped to the SONET/SDH network interfaces or to external LIUs via a parallel PDH interface.
Europa supports a flexible mapping from SPI-3<-> SONET/SDH, SPI-3<-> PDH interface or PDH interface <-> SONET/SDH.
The SONET/SDH interfaces include framers, pointer processors and complete TOH and POH processing. The SONET/SDH
interfaces support hardware-based SONET/SDH automatic protection switching (APS) and SDH Multiplex Section Protection
(MSP) for UPSR/SNCP rings, Linear and P2P. The STS/AU, TU3 and VT/TU cross-connects are provided for ADM and Terminal
applications, flexible channel assignment, channel re-arrangement, protection switching, diagnostics and loopbacks.
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© 2007 Arrive Technologies All Rights Reserved
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protocol framer, mapper, processor and L2 termination
programmable channelized network interfaces with
integrated SerDes w/CDR, full TOH processing and
flexible SONET/SDH multiplexing to the nxDS0 level
framers and STS/VC, TU3 and VT/TU cross-connects
supporting full ADM and Terminal capabilities
and encapsulated by GFP/HDLC/Cisco-
HDLC/PPP/BCP/LAPS/ATM
and Multilink Point-to-Point Protocol (ML PPP) in
combination with a Network/Access Processor
SONET/SDH, E1, DS1, J1, E3, DS3 VCAT and LCAS in
compliance with G.7043 over 672/504 DS1/E1/J1,
either VT/TU or M13/E13 mapped plus 24 DS3/E3s
protection switching (APS) and SDH Multiplex Section
Protection (MSP) for UPSR/SNCP rings, Linear and P2P
major DSU vendors: Quickeagle (DigitalLink), Kentrox,
Adtran, Verilink and Larscom (CSU/DSUs)
Any Service Any Port - ASAP linecards
Channelized PDH and SONET/SDH linecards
Multi-Service Edge Switches and Routers
Radio Network Controllers
Very high-density Ethernet over PDH/SONET/SDH
Wireless Backhaul Aggregation Platforms
Multi-Service Provisioning Platforms
1.244Gbps aggregate capacity deep channelized multi-
Provides four OC-12/3 or STM-4/1 independently
Includes 672/504 DS1/E1 and 24 DS3/E3 multi-
Supports 2048 individual channels, flexibly mapped
Supports Frame Relay, Multilink Frame Relay (ML FR)
Supports GFP-F encapsulated Ethernet over
Supports hardware-based SONET/SDH automatic
Subrate and scrambling supported for the following
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Deep Channelization Multi-Protocol Processor
Rev. 2.0 – July 2008
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Backplane
Ethernet
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Router
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Processor
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SPI3
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RLDRAM2
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AT2450 Preliminary Short Data Sheet
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OC-12/3
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DS1/E1/J1
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SFP XCVR
SFP XCVR
SFP XCVR
SFP XCVR
672/504
SFP XCVR
SFP XCVR
SFP XCVR
SFP XCVR
DS3/E3
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LIUs
LIUs
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SONET/SDH
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UPSR
P2P
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PDH
Page 1

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at2450 Summary of contents

Page 1

... Packet Processor Router Packet Backplane L2+ Packet Processor Ethernet Switch Packet Backplane AT2450 Preliminary Short Data Sheet / / ...

Page 2

... Asynchronous DS1/E1s via internal framers Provides channelization to DS0/E0 (56K or 64K), − including multiple channel groupings per DS1/E1 and fractional DS1/ AT2450 Preliminary Short Data Sheet ...

Page 3

... High Order VCAT/LCAS Processor  ZBT SRAM Interface ZBT SRAM (512kx36 AT2450 Preliminary Short Data Sheet BITS Timing  Host CPU Bus  Clock     Synthesizer/ Data Link uP Redundancy Controller Interface     24 M13/E13 672/504 PDH ...

Page 4

... BIP-8 error counts (Path-Parity Errors) Far-End Block Error (FEBE) counts E3 alarm/event detection: AIS, LOF, RAI, OOF, FERF AT2450 Preliminary Short Data Sheet Derived from corresponding receive DS3 Derived from any of SONET/SDH lines ...

Page 5

... Frame drop/discard event counters − Idle frame counter on receive − Transmit underrun counter − Transmit unexpected length error counter − Out of frame delineation event − AT2450 Preliminary Short Data Sheet ...

Page 6

... Optional discard or transfer error packet through SPI-3 system interface Provides status bus for queue visibility to handle flow control including full, satisfied, hungry and starving statuses AT2450 Preliminary Short Data Sheet ...

Page 7

... SONET/SDH Remote Line Loopback (14) SONET/SDH Local Line Loopback (15) Full SPI Bus Remote Loopback (16) Full SPI Bus Local Loopback All AIS functions are supported outside the loopback path AT2450 Preliminary Short Data Sheet ...

Page 8

... DS3 VCAT/LCAS Non-VCAT/LCAS Decapsulation Configuration Rx 24xDS3 Subrate and Status Memory (ECC) NxDS0 De-Map AT2450 Preliminary Short Data Sheet Performance OAM Counters, Insertion Alarm (ECC) ATM/PLCP Encapsulation 2048-channel GFP FIFO Per-channel 2048-channel 2048-channel Configuration (FIFO size and Status ...

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