at2450 Arrive Technologies, Inc., at2450 Datasheet - Page 2

• Manufacturer Part Number: at2450
• Description: Deep Channelization Multi-protocol Processor
• Manufacturer: Arrive Technologies, Inc.

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© 2007 Arrive Technologies All Rights Reserved
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network interfaces for 4xOC-12/3 or STM-4/1s with
loop-timed capability
loopbacks with BERT and detection capabilities
protection switching (APS) and SDH Multiplex Section
Protection (MSP) for UPSR/SNCP rings, Linear and P2P
lines)
VT/TU levels allows flexible line or local loopbacks for
all PDH payloads
channelized down to DSn streams
against Soft Errors
Soft Errors
(internal clock) or loop timing (recovered from
SONET/SDH network or PDH tributary) or BITS
tolerance requirements
available from Arrive for interfacing with commercial
DS3/E3/DS1/E1 LIUs
channel framer engine. Each channel can be
programmed for DS1, E1 or J1 with any of the
supported framing formats. The channel capacity
ranges from 504 to 672 based on the 2xOC-12/STM4
mapping capacity
randomly assigned to any of the 2048 nxDS0, 672/504
DS1/J1/E1, 24 DS3s/E3, 336 VCAT channels limited by
the 2xOC-12/STM-4 aggregate bandwidth and channel
limits
Provides independently-programmable, channelized
Flexible diagnostic via network side or line side
High and low-order path overhead (POH) processor
Supports hardware-based SONET/SDH automatic
BER monitor for SONET/SDH lines (including PDH
BER monitor for high and low-order POH
SONET/SDH overhead add/drop port
SONET/SDH cross connect at the STS/AU, TU3 and
Parallel 622Mbps Telecom Bus for STS-12 deep
Provides ECC on all critical internal RAMs to protect
Supports ECC on all external RAMs to protect against
Clock synthesis and network synchronization for local
Meets Telcordia and ITU Jitter generation and
External PDH interface Mux/DeMux FPGA design is
DS1/E1 framers are implemented with a 672/504
The 2048 data encapsulation channels can be
Implemented in .13u TSMC process
Europa is provided in a FCBGA 1296 package
Estimated power consumption is 6w
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Deep Channelization Multi-Protocol Processor
Rev. 2.0 – July 2008
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Quickeagle (DigitalLink), Kentrox, Adtran, Verilink and
Larscom (CSU/DSUs)
J1)
<-> AU-4 <-> TUG-3 <-> TUG-2 <-> TU-11 <-> VC-11
<-> DS1
Supports termination of 2048 channels
Supports un-channelized and channelized DS3/E3
Supports DS3 Subrate and Scrambling interoperable with
Supports DS1 clear-channel, framed fractional (including
Supports E1 clear-channel, framed fractional and unframed
Provides channelization to DS1 to/from SONET:
Provides channelization to DS1 to/from SDH:
Provides channelization to E1 to/from SONET:
Provides channelization to E1 to/from SDH:
Provides channelization to J1 to/from SDH:
Provides channelization to DS3 to/from SONET:
STS-12 <-> STS-1 <-> DS3/E3
Provides channelization to DS3 to/from SDH:
Supports 16128 DS0s over up to 2048 NxDS0/E0 channels
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to DS1 (M13 and C-bit framing) mapped into:
to E1 (M13 framing) mapped into:
12 <-> STS-1 <-> DS3 <-> E1
mapping: STM-4 <-> AU-4 <-> TUG-3 <-> TUG-2
mapping: STM-4 <-> AU-3 <-> VC-3 <-> TUG-2
<-> TU-11<-> VC-11 <-> J1
<-> DS3/E3
NxDS0/E0 channels where N=1-24 for DS1 and
N=1-31 for E1
directly or derived from converted Asynchronous
DS1/E1s via internal framers
including multiple channel groupings per DS1/E1
and fractional DS1/E1
Programmable to allow for other subrate methods
Support for VT1.5 mapping:
STS-12 <-> STS-1 <-> VT1.5 <-> DS1
Support for asynchronous DS3, channelized down
STS-12 <-> STS-1 <-> DS3 <-> DS1
Support for VT2 mapping:
STS-12 <-> STS-1 <-> VT Group <-> VT2 <-> E1
Support for asynchronous DS3, channelized down
Support for ITU-T G.707 (SDH CEPT/ETSI) VC-12
<-> TU-12 <->VC-12 <-> E1
Support for ITU-T G.707 (SDH-ANSI) VC-11
STM-4 <-> AU-3 <-> VC-3 <-> DS3/E3
STM-4 <-> AU-4 <-> TUG-3 <-> TU-3 <-> VC-3
Each DS1/E1 may be further channelized into
DS0s are extracted from Byte Synchronous VT/TUs
Provides channelization to DS0/E0 (56K or 64K),
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AT2450 Preliminary Short Data Sheet
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VIETNAM
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STM-4
STS-