at2450 Arrive Technologies, Inc., at2450 Datasheet - Page 6

• Manufacturer Part Number: at2450
• Description: Deep Channelization Multi-protocol Processor
• Manufacturer: Arrive Technologies, Inc.

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© 2007 Arrive Technologies All Rights Reserved
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channel
data channels
Virtual Concatenation for STS/VC and VT/TU level
with G.7043
as in ITU-T G.7042 with hitless addition/removal and
fault isolation
Xv support
for VC-3-Xc (X=1-24), VC-4-Xc (X=1-8); low-order for
VC-2-Xc (X=1-21), VC12-Xc (X=1-28), VC-11-Xc (X=1-
7)
4-Xv (X=1-8); low-order for VC-2-Xv (X=1-21), VC-12-
Xv (X=1-63), VC-11-Xv (X=1-64)
Nx44736 (N=1-8)
with G.8040, X.85/86, G.804 and IEEE 802.6
SONET/SDH
Various statistic events per ATM data channel
Various statistic events per HDLC/PPP/BCP/LAPS data
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STS/VC, VT/TU, E1/DS1/E3/DS3 termination via 2048
Supports standard-based Contiguous, any Random and
Supports E1/DS1/E3/DS3 VCAT and LCAS in compliance
Supports up to 336 VCGs for VCAT termination
Complies with Link Capacity Adjustment Scheme (LCAS)
TUG-3 SDH concatenation with both VC-4-Xv and VC-3-
Contiguous and Random Concatenation with high-order
SONET/SDH with high-order for VC-3-Xv (X=1-24), VC-
PDH VCAT for Nx1544, Nx2048 (N=1-16), Nx34368,
Data mapping over DS1/J1/E1/DS3/E3 in compliance
EoPDH and legacy data mapping-over-PDH and over
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receive
Good cell counters on transmit and receive
HEC uncorrected error counters
Single bit HEC error correction counter
Cell drop/discard event counters
Idle cell counter on receive
Transmit underrun counter
Out of cell delineation (OCD) event
Loss of cell delineation (LCD) event
Receive PLCP BIP errors
Receive PLCP Remote Alarm Detected event
Receive PLCP Out of Frame event
Good frame counters on transmit and receive
FCS error counters
Abort sequence detection counter
Frame length violation counters on transmit and
Frame drop/discard event counters
Transmit underrun counter
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Deep Channelization Multi-Protocol Processor
Rev. 2.0 – July 2008
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256ms using an external buffer via RLDRAM2
for DS1s, 256ms for E1/E3s, and 217ms for DS3s
VCAT channel to permit short paths and long international
paths
(excluding ECC), Europa can de-skew
channels over 8 logical ports for transporting data over
SONET/SDH
ID
maximum packet size supported is 15KB
priority queues per channel
system interface
control including full, satisfied, hungry and starving
statuses
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Terminates 16128xDS0 via 2048 data channels
Accommodates a SONET/SDH VCAT differential delay of
Accommodates a PDH VCAT differential delay of 384ms
Optimized low latency in VCAT de-skew
On-the-fly programmable differential delays for each
Supports 256Mbits and 512Mbits RLDRAM2
As small as 256Mbits of RLDRAM2 configuration
SPI-3 interface supports a maximum of 2048 data
Supports interface clock rate from 52MHz to 104MHz
Provides 8/16/32-bit interface bus width
Programmable 64/128-byte transfer size
Provisioning Pre-pended Tag for carrying 11-bit channel
Dynamic link multiple block buffer to store larger packet;
2K queues for Rx direction
4K queues for Tx direction with low-priority and high-
Optional discard or transfer error packet through SPI-3
Provides status bus for queue visibility to handle flow
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and fractional DS1/E1
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Supports Nx64Kbps and Nx56Kbps
Supports multiple channel grouping per DS1/E1
Supports contiguous and non-contiguous NxDS0
Supports NxDS0 BERT including
Supports NxDS0 loopback detection/insertion
+/- 64 ms for 512 VC-11/VT-1.5s
+/- 85 ms for full 24 VC-3/STS-1s
+/- 85 ms for full 24 E3s
+/- 72 ms for full 24 DS3s
+/- 64 ms for 512 E1s
+/- 96 ms for 512 DS1s
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QRSS, PRBS 9/11/15/20/23 (inverted or
not), DDS1/2/3/4/5, Fix 3 in 28, Fix 1 in 8,
DALY/55 Octet
A configurable fixed pattern which is
selectable from 1-bit to 32-bit
Inband user-designed loopcode
Inband X
Loopcode pattern can be detected/inserted
from/to 64Kbps or 56Kbps group
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AT2450 Preliminary Short Data Sheet
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+ 1 loopcode (T1.403-1999)
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