is42s16160g-7tli Integrated Silicon Solution, Inc., is42s16160g-7tli Datasheet

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G 32Meg x 8,  16Meg x16  256Mb SYNCHRONOUS DRAM FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – ( full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G DEVICE OVERVIEW The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V and 3.3V V memory systems containing 268,435,456 ddq bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is orga- nized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G PIN CONFIGURATIONS 54 pin TSOP - Type II  for x8 PIN DESCRIPTIONS A0-A12 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O CLK System Clock Input CKE Clock Enable Chip Select CS RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, Inc. — www.issi.com Rev.  00B ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G PIN CONFIGURATIONS 54 pin TSOP - Type II  for x16 PIN DESCRIPTIONS A0-A12 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command Column Address Strobe Command CAS DQ0 2 53 DQ15 ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G PIN CONFIGURATION 54-ball TF-BGA for x8 (Top View) (8. 8.00 mm Body, 0.8 mm Ball Pitch) package code VSS DQM G A12 VSS PIN DESCRIPTIONS A0-A12 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G PIN CONFIGURATION 54-ball TF-BGA for x16 (Top View) (8. 8.00 mm Body, 0.8 mm Ball Pitch) package code VSS B DQ14 C DQ12 D DQ10 E DQ8 F DQMH G A12 VSS PIN DESCRIPTIONS A0-A12 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G PIN FUNCTIONS   Symbol    Type  A0-A12 Input Pin BA0, BA1 Input Pin Input Pin CAS CKE Input Pin CLK Input Pin CS Input Pin DQML, Input Pin DQMH DQM Input Pin DQ -DQ or Input/Output RAS Input Pin WE Input Pin V P ower Supply Pin ddq V P ower Supply Pin ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A9 (x8); A0-A8 (x16) provides the starting column loca- tion. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. W hen the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ’s read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ’ ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G COMMAND TRUTH TABLE   CKE    Function       n – 1   n   Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit Note: H Valid Data CKE n – RAS CAS × × × × × × ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G FUNCTIONAL TRUTH TABLE  Current State  CS RAS CAS WE   Idle Row Active L L ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G FUNCTIONAL TRUTH TABLE Continued: Current State  CS RAS CAS WE   Read with auto H × × Precharging Write with Auto H × × Precharge L ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G FUNCTIONAL TRUTH TABLE Continued: Current State  CS RAS CAS WE   Write Recovering H × × Write Recovering H × × with Auto Precharge L L ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G CKE RELATED COMMAND TRUTH TABLE     Current State  Operation  Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t rc Idle After t rc Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle Illegal Illegal Exit clock suspend next cycle Maintain clock suspend Power-Down (P.D.) INVALID, CLK ( would exit P.D. ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G STATE DIAGRAM Mode Register Set Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON Integrated Silicon Solution, Inc. — www.issi.com Rev.  00B 11/24/2010 SELF SELF exit MRS IDLE CKE CKE ACT CKE ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G ABSOLUTE MAXIMUM RATINGS   Symbol  Parameters  V Maximum Supply Voltage dd max V Maximum Supply Voltage for Output Buffer ddq max V Input Voltage in V Output Voltage out P Allowable Power Dissipation d max I output Shorted Current cs T operating Temperature opr T Storage Temperature stg Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G DC ELECTRICAL CHARACTERISTICS 1   Symbol Parameter i Operating Current (1) dd1 i Precharge Standby Current dd2p (In Power-Down Mode) i Precharge Standby Current dd2ps (In Power-Down Mode) i Precharge Standby Current (2) dd2n (In Non Power-Down Mode) I Precharge Standby Current dd2ns (In Non Power-Down Mode) i Active Standby Current dd3p (Power-Down Mode) i Active Standby Current dd3ps (Power-Down Mode) i Active Standby Current (2) dd3n (In Non Power-Down Mode) I Active Standby Current dd3ns (In Non Power-Down Mode) i Operating Current dd4 i Auto-Refresh Current dd5 i Self-Refresh Current ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G AC ELECTRICAL CHARACTERISTICS      Symbol  Parameter  t Clock Cycle Time ck3 t ck2 t Access Time From CLK ac3 t ac2 t CLK HIGH Level Width ch t CLK LOW Level Width cl t Output Data Hold Time oh3 t oh2 t Output LOW Impedance Time lz t Output HIGH Impedance Time CAS Latency = 3 hz3 t hz2 t Input Data Setup Time ( Input Data Hold Time ( Address Setup Time ( Address Hold Time ( CKE Setup Time ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G OPERATING FREQUENCY / LATENCY RELATIONSHIPS  SYMBOL  PARAMETER  — Clock Cycle Time — Operating Frequency t Active Command To Read/Write Command Delay Time rcd RAS Latency (t rac rcd cac t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ras t Command Period (PRE to ACT Command Period (ACT[0] to ACT [1]) ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G AC TEST CONDITIONS  Input Load t CH 3.0V 1.4V CLK CMS CMH 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS   Parameter    AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level 20 Output Load Output t AC 1.4V Integrated Silicon Solution, Inc. — www.issi.com 1.4V 50Ω 50Ω ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G FUNCTIONAL DESCRIPTION The 256Mb SDRAMs are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G INITIALIzE AND LOAD MODE REGISTER CLK CKS CKH CKE CMS CMH CMS CMH COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G AUTO-REFRESH CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com Rev.  ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks Notes: 1. Self-Refresh Mode is not supported for A2 grade with Ta > 85 ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. MODE REGISTER DEFINITION BA1 BA0 A12 A11 A10 ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge The DQs will start driving as a result of the clock edge one cycle earlier ( 1), and provided that the relevant access times are met, the data will be valid by clock edge ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the t specification. Minimum t should be divided by rcd rcd ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the fol- lowing illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. Note that part of the row precharge time is rp hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ Integrated Silicon Solution, Inc. — www.issi.com Rev.  00B ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP READ BANK, COL n+1 D OUT OUT T2 T3 ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev.  00B 11/24/2010 READ READ READ BANK, BANK, BANK, COL b ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - BURST NOP NOP NOP TERMINATE n+1 D OUT OUT BURST ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK 0 DQ ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11, A12 ROW COLUMN A10 ROW BA0, BA1 BANK ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP PRECHARGE BANK (a or all n+1 D n+2 D ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A9 COLUMN ADDRESS A11, A12 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS Note "Don't Care" for x16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS CLK WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ADDRESS COL n DON'T CARE T0 T1 ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL Integrated Silicon Solution, Inc. — www.issi.com Rev.  00B 11/24/2010 NOP ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS NOP NOP NOP PRECHARGE BANK (a or all) t DPL D n CLK BURST WRITE TERMINATE COMMAND BANK, ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = Full Page 2) x16: A9, A11, and A12 = " ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G WRITE - DQM OPERATION T0 t CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW BA0, BA1 BANK DQ t Notes: 1) Burst Length = 4 2) x16: A9, A11, and A12 = "Don't Care" ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G ALTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK 0 ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time Clock Suspend During WRITE Burst T0 CLK CKE INTERNAL CLOCK COMMAND NOP ADDRESS DQ Clock Suspend During READ Burst ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G CLOCK SUSPEND MODE CLK CKS CKH CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/DQML DQMH A0-A9, A11, A12 COLUMN m ( A10 BA0, BA1 BANK DQ Notes: 1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled. ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE rp command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/DQML DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles All banks idle, enter Precharge all ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI READ  ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t is met, where t begins when the READ to bank m is dpl registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G SINGLE WRITE WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM/DQML, DQMH A0-A9, A11, A12 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD ...

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... IS42S83200G-7BLI   F requency  Speed (ns)  Order Part No.  166 MHz 6 IS42S16160G-6TLI IS42S16160G-6BLI 143 MHz 7 IS42S16160G-7TLI IS42S16160G-7BLI 60  = 3.3V DD Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free 54-Ball BGA, Lead-free Package 54-Pin TSOPII, Lead-free 54-Ball BGA, Lead-free 54-Pin TSOPII, Lead-free 54-Ball BGA, Lead-free Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free 54-Ball BGA, Lead-free ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G Automotive Range A1: -40°C to +85°C Frequency  Speed (ns)  Order Part No.  166 MHz 6 IS45S83200G-6TLA1 143 MHz 7 IS45S83200G-7TLA1 IS45S83200G-7CTNA1 IS45S83200G-7BLA1   F requency  Speed (ns)  Order Part No.  166 MHz 6 IS45S16160G-6TLA1 IS45S16160G-6BLA1 143 MHz ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G 62 Integrated Silicon Solution, Inc. — www.issi.com Rev.  00B 11/24/2010 ...

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... IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G Integrated Silicon Solution, Inc. — www.issi.com Rev.  00B 11/24/2010 63 ...