is42s16800a-7tli Integrated Silicon Solution, Inc., is42s16800a-7tli Datasheet

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... Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 1-800-379-4774 ISSI PRELIMINARY INFORMATION JANUARY 2005 IS42S16800A IS42S32400A 2M x16x4 Banks 1M x32x4 Banks 54-pin TSOPII 86-pin TSOPII -6 -7 -10 Unit ...

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... IS42S81600A, IS42S16800A, IS42S32400A DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V and 3.3V V memory systems containing 134,217,728 DDQ bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is orga- nized as 4,096 rows by 512 columns by 16 bits. ...

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... IS42S81600A, IS42S16800A, IS42S32400A PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address I/O0 to I/O7 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, Inc. — ...

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... IS42S81600A, IS42S16800A, IS42S32400A PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address I/O0 to I/O15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS ...

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... IS42S81600A, IS42S16800A, IS42S32400A PIN CONFIGURATIONS 86 pin TSOP - Type II for x32 I/O1 I/ I/O3 I/ I/ DQM0 WE CAS RAS CS A11 BA0 BA1 A10 DQM2 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 V DD ...

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... IS42S81600A, IS42S16800A, IS42S32400A PIN FUNCTIONS Symbol Type A0-A11 Input Pin BA0, BA1 Input Pin CAS Input Pin CKE Input Pin CLK Input Pin CS Input Pin DQML, Input Pin DQMH DQM0-DQM3 Input Pin DQM Input Pin RAS Input Pin WE Input Pin V Power Supply Pin ...

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... IS42S81600A, IS42S16800A, IS42S32400A GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A9 (x8); A0-A8 (x16); A0-A7 (x32) provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst ...

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... IS42S81600A, IS42S16800A, IS42S32400A COMMAND TRUTH TABLE CKE Function Symbol n – 1 Device deselect H No operation H Burst stop H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate H Precharge select bank H Precharge all banks H Mode register set H Note: H Valid Data. ...

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... IS42S81600A, IS42S16800A, IS42S32400A CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle Self refresh entry Idle Power down entry Idle Deep power down entry Self refresh exit ...

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... IS42S81600A, IS42S16800A, IS42S32400A FUNCTIONAL TRUTH TABLE RAS RAS RAS CAS RAS RAS CAS CAS CAS CAS Idle Row Active ...

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... IS42S81600A, IS42S16800A, IS42S32400A FUNCTIONAL TRUTH TABLE Continued RAS RAS CAS RAS RAS RAS CAS CAS CAS CAS Read with auto H × × Precharging Precharge Precharging Write with Auto H × ...

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... IS42S81600A, IS42S16800A, IS42S32400A FUNCTIONAL TRUTH TABLE Continued RAS CAS RAS RAS CAS CAS CAS CS CS RAS RAS CAS Write Recovering H × × Write Recovering H × × with Auto ...

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... IS42S81600A, IS42S16800A, IS42S32400A FUNCTIONAL TRUTH TABLE Continued: Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H). 2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 3. Illegal if tRCD is not satisfied. 4. Illegal if tRAS is not satisfied. ...

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... IS42S81600A, IS42S16800A, IS42S32400A STATE DIAGRAM Extended Mode Register Set Mode Register Set Deep Power Down Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON 14 SELF EMRS SELF exit MRS IDLE CKE DPD CKE DPD Exit ACT ...

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... IS42S81600A, IS42S16800A, IS42S32400A ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG Notes: 1 ...

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... IS42S81600A, IS42S16800A, IS42S32400A DC ELECTRICAL CHARACTERISTICS Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level OH V Output Low Voltage Level OL (1,2) I Operating Current DD1 I Precharge Standby Current DD2P I (In Power-Down Mode) ...

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... IS42S81600A, IS42S16800A, IS42S32400A AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 (4) t Access Time From CLK AC3 t AC2 t CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH3 t OH2 t Output LOW Impedance Time LZ t Output HIGH Impedance Time ...

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... IS42S81600A, IS42S16800A, IS42S32400A OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command CCD t CKE to clock disable or power-down entry mode CKED t CKE to clock enable or power-down exit setup mode PED t DQM to input data delay DQD ...

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... IS42S81600A, IS42S16800A, IS42S32400A AC TEST CONDITIONS Input Load t CHI 3.0V 1.5V CLK 3.0V INPUT 1. OUTPUT 1.5V AC TEST CONDITIONS Parameter AC High Level Input Voltage/Low Level Input Voltage Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S81600A, IS42S16800A, IS42S32400A FUNCTIONAL DESCRIPTION The 128Mb SDRAMs are quad-bank DRAMs which oper- ate at 2.5V or 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. ...

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... IS42S81600A, IS42S16800A, IS42S32400A INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µ ...

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... IS42S81600A, IS42S16800A, IS42S32400A AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High Auto NOP NOP Refresh t RP Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S81600A, IS42S16800A, IS42S32400A SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks refresh mode Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S81600A, IS42S16800A, IS42S32400A REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power ...

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... IS42S81600A, IS42S16800A, IS42S32400A BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...

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... IS42S81600A, IS42S16800A, IS42S32400A CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...

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... IS42S81600A, IS42S16800A, IS42S32400A CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank) ...

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... IS42S81600A, IS42S16800A, IS42S32400A READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...

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... IS42S81600A, IS42S16800A, IS42S32400A same bank. The PRECHARGE command should be is- sued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to PRECHARGE diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst ...

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... IS42S81600A, IS42S16800A, IS42S32400A RW1 - READ TO WRITE CLK DQM COMMAND ADDRESS DQ RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE T0 CLK DQM COMMAND READ BANK, ADDRESS COL READ NOP NOP BANK, COL NOP NOP NOP OUT Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S81600A, IS42S16800A, IS42S32400A CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00C 01/20/ NOP NOP ...

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... IS42S81600A, IS42S16800A, IS42S32400A RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - READ READ READ BANK, BANK, BANK, COL b COL m COL OUT OUT CAS Latency - ...

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... IS42S81600A, IS42S16800A, IS42S32400A READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00C 01/20/ NOP NOP ...

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... IS42S81600A, IS42S16800A, IS42S32400A ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD ...

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... IS42S81600A, IS42S16800A, IS42S32400A READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD ...

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... IS42S81600A, IS42S16800A, IS42S32400A READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD ...

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... IS42S81600A, IS42S16800A, IS42S32400A READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00C 01/20/ NOP ...

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... IS42S81600A, IS42S16800A, IS42S32400A WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...

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... IS42S81600A, IS42S16800A, IS42S32400A WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00C 01/20/ CLK WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ...

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... IS42S81600A, IS42S16800A, IS42S32400A WRITE TO READ T0 CLK COMMAND WRITE BANK, ADDRESS COL Latency = 2 WRITE TO PRECHARGE (TWR @ TCK T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL NOP READ NOP BANK, COL b D n+1 IN 15NS NOP NOP PRECHARGE ...

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... IS42S81600A, IS42S16800A, IS42S32400A WRITE to PRECHARGE ( CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00C 01/20/ 15ns NOP NOP PRECHARGE BANK (a or all ...

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... IS42S81600A, IS42S16800A, IS42S32400A WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = Full Page 2) X16: A9 and A11 = " ...

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... IS42S81600A, IS42S16800A, IS42S32400A WRITE - DQM OPERATIOON T0 t CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ Notes: 1) Burst Length = 4 2) X16: A9 and A11 = "Don't Care" ...

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... IS42S81600A, IS42S16800A, IS42S32400A ALTERNATING BANK WRITE ACCESS CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD ...

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... IS42S81600A, IS42S16800A, IS42S32400A CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...

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... IS42S81600A, IS42S16800A, IS42S32400A CLOCK SUSPEND MODE CLK CKS CKH CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/DQML DQMH/DQM0 (2) A0-A9, A11 COLUMN A10 BA0, BA1 BANK DQ Notes: 1) CAS latency = 2, Burst Length = 2 2) X16: A9 and A11 = "Don't Care" ...

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... IS42S81600A, IS42S16800A, IS42S32400A PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE RP command is issued. Input A10 determines whether one or ...

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... IS42S81600A, IS42S16800A, IS42S32400A POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/DQML DQMH/DQM0-3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all All banks idle, enter active banks power-down mode 48 T1 ...

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... IS42S81600A, IS42S16800A, IS42S32400A BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length ...

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... IS42S81600A, IS42S16800A, IS42S32400A WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t where t begins when the READ to bank m is registered. ...

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... IS42S81600A, IS42S16800A, IS42S32400A SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) X16: A9 and A11 = " ...

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... IS42S81600A, IS42S16800A, IS42S32400A READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC ...

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... IS42S81600A, IS42S16800A, IS42S32400A SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD t RAS ...

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... IS42S81600A, IS42S16800A, IS42S32400A READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC ...

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... IS42S81600A, IS42S16800A, IS42S32400A SINGLE WRITE WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) X16: A9 and A11 = " ...

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... IS42S81600A, IS42S16800A, IS42S32400A SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) X16: A9 and A11 = " ...

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... IS42S81600A, IS42S16800A, IS42S32400A WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC ...

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... IS42S81600A, IS42S16800A, IS42S32400A WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/DQML DQMH/DQM0 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC ...

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... IS42S81600A, IS42S16800A, IS42S32400A ORDERING INFORMATION - V Commercial Range Frequency Speed (ns) Order Part No. 166 MHz 6 IS42S81600A-6T 143 MHz 7 IS42S81600A-7T 100 MHz 10 IS42S81600A-10T Frequency Speed (ns) Order Part No. 166 MHz 6 IS42S16800A-6T 143 MHz 7 IS42S16800A-7T 100 MHz 10 IS42S16800A-10T Frequency Speed (ns) Order Part No. 166 MHz ...

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... IS42S32400A-10TL ORDERING INFORMATION - V Industrial Range: - Frequency Speed (ns) Order Part No. 143 MHz 7 IS42S81600A-7TLI 100 MHz 10 IS42S81600A-10TI Frequency Speed (ns) Order Part No. 143 MHz 7 IS42S16800A-7TLI 100 MHz 10 IS42S16800A-10TLI Frequency Speed (ns) Order Part No. 143 MHz 7 IS42S32400A-7TLI 100 MHz 10 IS42S32400A-10TLI 60 = 3.3V DD Package 54-Pin TSOPII, Lead-free ...

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... C 0.12 0.21 D 22.02 22.42 E1 10.03 10.29 E 11.56 11.96 e 0.80 BSC L 0.40 0.60 L1 — — ZD 0.71 REF α 0° 8° Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 01/28/02 N/2 Inches Min Max No. Leads (N) — 0.047 0.002 0.006 — — 0.012 0.018 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 — ...