is42s16800f-7tli Integrated Silicon Solution, Inc., is42s16800f-7tli Datasheet
is42s16800f-7tli
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is42s16800f-7tli Summary of contents
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... Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 OVERVIEW ISSI 's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture ...
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... REFRESH CONTROLLER SELF REFRESH CONTROLLER 16 REFRESH COUNTER 4096 4096 4096 12 ROW ADDRESS BUFFER 12 BANK CONTROL LOGIC Integrated Silicon Solution, Inc. — www.issi.com DQML DQMH DATA IN BUFFER 0- DDQ DATA OUT BUFFER Q 16 ...
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... PIN DESCRIPTIONS A0-A11 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O CLK System Clock Input CKE Clock Enable Chip Select CS RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 DQ0 2 53 DQ7 ...
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... A10 Write Enable DQML x16 Lower Byte, Input/Output Mask DQMH x16 Upper Byte, Input/Output Mask V Power dd Vss Ground V Power Supply for I/O Pin ddq Vss Ground for I/O Pin Connection Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 ...
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... Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select Row Address Strobe Command RAS Column Address Strobe Command CAS Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 VSS DQ15 VSSQ VDDQ DQ14 DQ13 VDDQ VSSQ DQ12 DQ11 VSSQ VDDQ DQ10 DQ9 VDDQ ...
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... For IS42/45S81600F only. Data on the Data Bus is latched on DQ pins during Write commands, and buffered for output after Read commands. RAS, in conjunction with CAS and WE, forms the device command. See the "Com- mand Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Com- mand Truth Table" item for details on device commands the output buffer power supply. ddq V is the device internal power supply the output buffer ground. ssq V is the device internal ground. ss Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 ...
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... AUTO PRECHARGE The AUTO PRECHARGE function ensures that the pre- charge is initiated at the earliest valid stage within a burst. This function allows for individual-bank precharge without requiring an explicit command. A10 to enable the AUTO Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 PRECHARGE function in conjunction with a specific READ or WRITE command. For each individual READ or WRITE command, auto precharge is either enabled or disabled. AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed ...
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... L H × × × × H × × × Integrated Silicon Solution, Inc. — www.issi.com A11 BA1 BA0 A10 × × × × × × × × × × × × ...
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... CKE TRUTH TABlE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit Note: H Valid Data Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 CKE n – RAS CAS × × × × × ...
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... NOP L X BST H BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA ACT L BA, A10 PRE/PALL H X REF/SELF L OC, BA MRS Integrated Silicon Solution, Inc. — www.issi.com Action Nop or Power Down (2) Nop or Power Down (2) Nop or Power Down ILLEGAL (3) ILLEGAL (3) Row activating Nop Auto refresh or Self-refresh (4) Mode register set Nop Nop Nop ...
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... H Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 Address Command × × DESL H x NOP L × BST H BA, CA, A10 READ/READA L BA, CA, A10 WRIT/ WRITA H BA, RA ...
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... DESL H × NOP L × BST × BA, CA, A10 READ/WRITE × BA, RA ACT/PRE/PALL ILLEGAL REF/MRS Integrated Silicon Solution, Inc. — www.issi.com Action Nop, Enter row active after tDPL Nop, Enter row active after tDPL Nop, Enter row active after tDPL Begin read (8) Begin new write ILLEGAL (3) ILLEGAL (3) ILLEGAL ILLEGAL Nop, Enter precharge after tDPL Nop, Enter precharge after tDPL Nop, Enter row active after tDPL ILLEGAL ...
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... Exit clock suspend next cycle Maintain clock suspend Notes High level low level High or low level (Don’t care). 2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 3. Power down and Self refresh can be entered only from the both banks idle state. 4. Must be legal command as defined in Operative Command Table. 5. Illegal not satisfied. srx Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 (1) CKE n ( (2) ...
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... SELF exit MRS IDLE CKE CKE ACT CKE Row Active CKE BST BST Read Write Read Write Precharge Integrated Silicon Solution, Inc. — www.issi.com Self Refresh REF CBR (Auto) Refresh Power Down Active Power Down Read CKE READ READ SUSPEND CKE ...
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... All voltages are referenced to Vss. CAPACITANCE CHARACTERISTICS Symbol Parameter C Input Capacitance: CLK in1 C Input Capacitance:All other input pins in2 C / Data Input/Output Capacitance:I/ Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 (1) Rating –0.5 to +4.6 –0.5 to +4.6 –0 – Com +70 Ind. -40 to +85 A1 -40 to +85 A2 ...
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... CKE ≤ 0.2V (Recommended Operation Conditions unless otherwise noted.) Test Condition 0V ≤ Vin ≤ with pins other than dd the tested pin at 0V Output is disabled, 0V ≤ Vout ≤ -2mA 2mA ol Integrated Silicon Solution, Inc. — www.issi.com - Unit 160 140 120 mA mA ...
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... C Com, Ind, A1 ref a (4096) T ≤ Notes: 1. The power-on sequence must be executed before starting memory operation. 2. measured with ns. If clock rising time is longer than 1ns The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between V 4. Self-Refresh Mode is not supported for A2 grade with T Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 (1,2,3) -5 Min. Max. 5 — CAS Latency = 3 10 — CAS Latency = 2 — 5 CAS Latency = 3 — 5.4 CAS Latency = 2 2 — ...
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... CAS Latency = 3 3 CAS Latency = CAS Latency = 3 3 CAS Latency = CAS Latency = 3 -1 CAS Latency = Integrated Silicon Solution, Inc. — www.issi.com -6 -7 UNITS 7.5 ns 166 143 MHz 100 133 MHz 3 3 cycle 2 2 cycle 6 6 cycle ...
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... AC TEST CONDITIONS Input load t CH 3.0V 1.4V CLK CMS CMH 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 Output load Output t AC 1.4V 1.4V 50Ω 50Ω Rating 1.4V 1.4V 19 ...
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... All banks must be precharged. This will leave all banks in an idle state after which at least two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is then ready for mode register programming. The mode register should be loaded prior to applying any operational command because it will power unknown state. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 ...
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... ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µs Min. Notes High at clock High time, all commands applied are NOP. 2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired. 3. JEDEC and PC100 specify three clocks. 4. Outputs are guaranteed High-Z after the command is issued. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 (1) Tn+1 To CMS CMH AUTO AUTO ...
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... A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. CAS latency = Auto NOP Refresh Integrated Silicon Solution, Inc. — www.issi.com Tn+1 To+1 Auto NOP ACTIVE Refresh ROW ROW BANK t RC DON'T CARE Rev. 00A 11/16/2010 ...
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... DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks refresh mode Note: 1. Self-Refresh Mode is not supported for A2 grade with T Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 CKS t RAS Auto NOP Refresh t RP ...
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... Reserved Operating Mode M8 M7 M6-M0 Mode 0 0 Defined Standard Operation — — — All Other States Reserved Mode Programmed Burst Length Single Location Access Integrated Silicon Solution, Inc. — www.issi.com Address Bus Mode Register (Mx) Burst Length M3=0 M3 ...
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... Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 ing that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 (x16) when the burst length is set to two; by A2-A8 (x16) when the burst length is set to four; and by A3-A8 (x16) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved ...
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... D OUT CAS Latency - READ NOP NOP NOP CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com CAS latency = 2 CAS latency = 3 100 200 100 166 133 143 OUT t OH DON'T CARE UNDEFINED Rev. 00A 11/16/2010 ...
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... EXAMPlE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3 CLK COMMAND Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 ACTIVATING SPECIFIC ROW WITHIN SPE- CIFIC BANK CLK CKE CS RAS ...
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... A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 ...
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... Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ Burst Termination diagram for each possible CAS latency; data element the last desired data element of a longer burst. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 29 ...
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... NOP n+1 D n+2 OUT OUT OUT NOP NOP NOP OUT CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com T5 T6 NOP WRITE BANK, COL DON'T CARE T4 T5 NOP WRITE BANK, COL DON'T CARE Rev ...
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... CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 NOP NOP NOP READ BANK, COL n+1 D OUT OUT ...
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... D b OUT OUT CAS Latency - READ READ READ NOP BANK, BANK, BANK, COL b COL m COL OUT Integrated Silicon Solution, Inc. — www.issi.com T4 T5 NOP NOP OUT OUT DON'T CARE T5 T6 NOP NOP OUT ...
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... T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 BURST NOP NOP NOP TERMINATE n+1 D OUT OUT T2 T3 ...
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... ROW ENABLE AUTO PRECHARGE ROW BANK 0 BANK OUT CAS Latency - BANK BANK 3 RCD Integrated Silicon Solution, Inc. — www.issi.com READ NOP ACTIVE COLUMN b (2) ROW ROW BANK 3 BANK ...
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... A10 ROW BA0, BA1 BANK BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = Full Page 2) x16: A9 and A11 = "Don't Care" x8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 READ NOP NOP NOP t CMH (2) ...
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... CL CH READ NOP NOP NOP t t CMS CMH COLUMN m (2) BANK OUT CAS Latency Integrated Silicon Solution, Inc. — www.issi.com NOP NOP NOP OUT OUT DON'T CARE UNDEFINED Rev ...
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... CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 NOP NOP NOP PRECHARGE BANK (a or all n+1 D n+2 D ...
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... Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncat- ing a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in WRITE Burst Termination, where data n is the last desired data element of a longer burst. Integrated Silicon Solution, Inc. — www.issi.com after the dpl of dpl is met. Rev. 00A 11/16/2010 ...
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... IS42/45S81600F, IS42/45S16800F WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYClES COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 CLK WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ADDRESS COL n DQ ...
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... NOP BANK, COL b D n+1 IN CAS Latency - NOP NOP PRECHARGE BANK (a or all) t DPL D n Integrated Silicon Solution, Inc. — www.issi.com T4 T5 NOP NOP b+1 OUT OUT DON'T CARE NOP ACTIVE NOP BANK a, ROW DON'T CARE Rev. 00A ...
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... IS42/45S81600F, IS42/45S16800F WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 NOP NOP PRECHARGE BANK (a or all) t DPL D n CLK BURST ...
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... CMS CMH (2) COLUMN m BANK Full page completed Integrated Silicon Solution, Inc. — www.issi.com T5 Tn+1 Tn+2 NOP NOP BURST TERM NOP DON'T CARE 11/16/2010 Rev ...
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... AS AH A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = 4 2) x16: A9 and A11 = "Don't Care" x8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 WRITE NOP NOP t t CMS CMH COLUMN m ...
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... DPL t - BANK 1 RCD Integrated Silicon Solution, Inc. — www.issi.com WRITE NOP NOP ACTIVE (2) COLUMN b ROW ROW BANK 1 BANK ...
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... Clock Suspend During READ Burst T0 CLK CKE INTERNAL CLOCK COMMAND READ BANK a, ADDRESS COL n DQ Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See following examples.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge ...
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... A11 = "Don't Care" CKH NOP NOP NOP m+1 OUT OUT Integrated Silicon Solution, Inc. — www.issi.com NOP WRITE NOP COLUMN n (2) BANK e DON'T CARE UNDEFINED Rev. 00A 11/16/2010 ...
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... The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting t ). See figure below. cks POWER-DOWN CLK CKE COMMAND All banks idle Enter power-down mode Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 PRECHARGE Command CLK CKE CS RAS CAS WE A0-A9, A11 A10 BA0, BA1 ...
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... CKS NOP NOP Input buffers gated off while in power-down mode Exit power-down mode Integrated Silicon Solution, Inc. — www.issi.com Tn+1 Tn+2 t CKS NOP ACTIVE ROW ROW BANK All banks idle DON'T CARE 11/16/2010 Rev. 00A ...
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... Page Active Internal States BANK m BANK n, ADDRESS COL a DQM DQ CAS Latency - 3 (BANK n) Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered ...
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... WRITE - AP NOP NOP BANK m WRITE with Burst of 4 Interrupt Burst, Write-Back Page Active BANK m, COL a Integrated Silicon Solution, Inc. — www.issi.com begins when the WRITE to bank dpl NOP NOP NOP Precharge BANK BANK m Precharge b+1 OUT ...
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... AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) x16: A9 and A11 = "Don't Care" x8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 NOP NOP READ NOP t t CMS ...
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... READ NOP NOP NOP t CMH (2) BANK m+1 OUT OUT CAS Latency Integrated Silicon Solution, Inc. — www.issi.com NOP NOP ACTIVE ROW ROW BANK m+2 D m+3 OUT OUT DON'T CARE t RP UNDEFINED Rev ...
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... DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) x16: A9 and A11 = "Don't Care" x8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 READ NOP NOP PRECHARGE t ...
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... CH READ NOP NOP NOP t CMH (2) BANK m+1 OUT OUT CAS Latency Integrated Silicon Solution, Inc. — www.issi.com PRECHARGE NOP ACTIVE ROW ALL BANKS ROW SINGLE BANK BANK BANK m+2 D m+3 OUT OUT t t ...
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... BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) x16: A9 and A11 = "Don't Care" x8: A11 = "Don't Care" must not be violated. ras Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 WRITE NOP NOP PRECHARGE t t CMS ...
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... WRITE NOP NOP PRECHARGE t CMS CMH (2) COLUMN m ALL BANKS SINGLE BANK BANK DPL (3) Integrated Silicon Solution, Inc. — www.issi.com NOP ACTIVE NOP ROW ROW BANK BANK t RP DON'T CARE Rev. 00A 11/16/2010 ...
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... BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 4 2) x16: A9 and A11 = "Don't Care" x8: A11 = "Don't Care" must not be violated. ras Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 WRITE NOP NOP NOP t ...
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... CH NOP NOP NOP t CMH ( Integrated Silicon Solution, Inc. — www.issi.com NOP NOP NOP ACTIVE ROW ROW BANK t t DPL RP DON'T CARE Rev. 00A 11/16/2010 ...
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... IS42S81600F-7TLI Frequency Speed (ns) Order Part No. 200 MHz 5 IS42S16800F-5TLI IS42S16800F-5BLI 166 MHz 6 IS42S16800F-6TLI IS42S16800F-6BLI 143 MHz 7 IS42S16800F-7TLI IS42S16800F-7BLI *Contact ISSI for Leaded parts support. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 = 3.3V DD Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free Package 54-Pin TSOPII, Lead-free 54-ball BGA, Lead-free 54-Pin TSOPII, Lead-free 54-ball BGA, Lead-free 54-Pin TSOPII, Lead-free ...
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... DD Package 54-pin TSOPII, Alloy42 leadframe plated with matte Sn 54-pin TSOPII, Alloy42 leadframe plated with matte Sn 54-pin TSOPII, Cu leadframe plated with NiPdAu Package 54-pin TSOPII, Alloy42 leadframe plated with matte Sn 54-ball BGA, SnAgCu balls 54-pin TSOPII, Alloy42 leadframe plated with matte Sn 54-pin TSOPII, Cu leadframe plated with NiPdAu 54-ball BGA, SnAgCu balls Package 54-pin TSOPII, Alloy42 leadframe plated with matte Sn 54-pin TSOPII, Cu leadframe plated with NiPdAu Package 54-pin TSOPII, Alloy42 leadframe plated with matte Sn 54-pin TSOPII, Cu leadframe plated with NiPdAu 54-ball BGA, SnAgCu balls Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 ...
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... IS42/45S81600F, IS42/45S16800F Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 61 ...
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... IS42/45S81600F, IS42/45S16800F 62 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 ...
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... IS42/45S81600F, IS42/45S16800F Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/16/2010 63 ...