is42s16800b-6tli Integrated Silicon Solution, Inc., is42s16800b-6tli Datasheet

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... ISSI 's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized as follows. IS42S81600B IS42S16800B 4M x8x4 Banks 2M x16x4 Banks 54-pin TSOPII 54-pin TSOPII KEY TIMING PARAMETERS ...

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... IS42S81600B, IS42S16800B DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V and 3.3V V memory systems containing 134,217,728 ddq bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is orga- nized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits ...

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... IS42S81600B, IS42S16800B PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O CLK System Clock Input CKE Clock Enable Chip Select CS RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, Inc. — ...

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... IS42S81600B, IS42S16800B PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable Chip Select CS RAS Row Address Strobe Command CAS ...

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... When DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be written to the device. WhenDQML or DQMH is HIGH, input data is masked and cannot be written to the device. For IS42S16800B only. For IS42S81600B only. Data on the Data Bus is latched on DQ pins during Write commands, and buffered for output after Read commands. RAS, in conjunction with CAS and WE, forms the device command. See the " ...

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... IS42S81600B, IS42S16800B GENERAl DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0- A9 (x8); A0-A8 (x16) provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst ...

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... IS42S81600B, IS42S16800B COMMAND TRUTH TABlE CKE Function n – 1 Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) ...

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... IS42S81600B, IS42S16800B CKE TRUTH TABlE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit ...

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... IS42S81600B, IS42S16800B FUNCTIONAl TRUTH TABlE Current State CS RAS CAS Idle Row Active Read ...

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... IS42S81600B, IS42S16800B FUNCTIONAl TRUTH TABlE Continued: Current State CS RAS CAS Read with auto H × × Precharging Write with Auto H × × Precharge ...

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... IS42S81600B, IS42S16800B FUNCTIONAl TRUTH TABlE Continued: Current State CS RAS CAS Write Recovering H × × Write Recovering H × × with Auto Precharge ...

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... IS42S81600B, IS42S16800B CKE RElATED COMMAND TRUTH TABlE Current State Operation Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t rc Idle After t rc Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle ...

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... IS42S81600B, IS42S16800B STATE DIAGRAM Mode Register Set BST Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 12/06/07 SELF SELF exit MRS REF IDLE CKE CKE ACT CKE Row Active ...

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... IS42S81600B, IS42S16800B ABSOlUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage dd max V Maximum Supply Voltage for Output Buffer ddq max V Input Voltage in V Output Voltage out P Allowable Power Dissipation d max I output Shorted Current cs T operating Temperature opr T Storage Temperature stg Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

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... IS42S81600B, IS42S16800B DC ElECTRICAl CHARACTERISTICS 1 Symbol Parameter i Operating Current (1) dd1 Precharge Standby Current dd2p (In Power-Down Mode) i Precharge Standby Current dd2ps mA (In Power-Down Mode) i Precharge Standby Current (2) dd2n mA (In Non Power-Down Mode) I Precharge Standby Current dd2ns mA (In Non Power-Down Mode) i Active Standby Current ...

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... IS42S81600B, IS42S16800B AC ElECTRICAl CHARACTERISTICS Symbol Parameter t Clock Cycle Time ck3 t ck2 t Access Time From CLK ac3 t ac2 t CLK HIGH Level Width chi t CLK LOW Level Width cl t Output Data Hold Time oh3 t oh2 t Output LOW Impedance Time lz t Output HIGH Impedance Time ...

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... IS42S81600B, IS42S16800B OPERATING FREQUENCY / lATENCY RElATIONSHIPS SYMBOl PARAMETER — Clock Cycle Time — Operating Frequency (CAS Latency = 3) t CAS Latency cac t Active Command To Read/Write Command Delay Time rcd t RAS Latency ( rac rcd cac t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ...

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... IS42S81600B, IS42S16800B AC TEST CONDITIONS Input load t CHI 3.0V 1.4V CLK 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level 18 Output load Output t AC 1.4V Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S81600B, IS42S16800B FUNCTIONAl DESCRIPTION The 128Mb SDRAMs are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits. ...

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... IS42S81600B, IS42S16800B INITIAlIzE AND lOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µ ...

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... IS42S81600B, IS42S16800B AUTO-REFRESH CYClE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S81600B, IS42S16800B SElF-REFRESH CYClE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks refresh mode CKS ≥ ...

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... IS42S81600B, IS42S16800B REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power ...

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... IS42S81600B, IS42S16800B BURST lENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...

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... IS42S81600B, IS42S16800B CAS latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...

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... IS42S81600B, IS42S16800B CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...

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... IS42S81600B, IS42S16800B READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...

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... IS42S81600B, IS42S16800B diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. Note that part of the row precharge time is rp hidden during the access of the last data element(s) ...

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... IS42S81600B, IS42S16800B RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 12/06/ NOP NOP NOP NOP t HZ ...

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... IS42S81600B, IS42S16800B CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP READ BANK, COL n+1 D OUT OUT NOP NOP ...

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... IS42S81600B, IS42S16800B RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 12/06/ READ READ READ BANK, BANK, BANK, COL b COL m COL ...

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... IS42S81600B, IS42S16800B READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - BURST NOP NOP NOP TERMINATE n+1 D OUT OUT BURST NOP NOP ...

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... IS42S81600B, IS42S16800B AlTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD ...

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... IS42S81600B, IS42S16800B READ - FUll-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD ...

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... IS42S81600B, IS42S16800B READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD ...

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... IS42S81600B, IS42S16800B READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP PRECHARGE BANK (a or all n+1 D n+2 D OUT OUT OUT ...

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... IS42S81600B, IS42S16800B WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A9 COLUMN ADDRESS A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS Note "Don't Care" for x16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...

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... IS42S81600B, IS42S16800B WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYClES COMMAND ADDRESS CLK WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ADDRESS COL n DON'T CARE CLK WRITE WRITE ...

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... IS42S81600B, IS42S16800B WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 12/06/ NOP READ NOP BANK, COL n+1 IN ...

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... IS42S81600B, IS42S16800B WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS NOP NOP NOP PRECHARGE BANK (a or all) t DPL D n CLK BURST WRITE TERMINATE COMMAND BANK, (ADDRESS) COL (DATA) ...

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... IS42S81600B, IS42S16800B WRITE - FUll PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = Full Page 2) X16: A9 and A11 = "Don't Care" ...

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... IS42S81600B, IS42S16800B WRITE - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = 4 2) X16: A9 and A11 = "Don't Care" ...

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... IS42S81600B, IS42S16800B AlTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BANK 0 BA0, BA1 ...

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... IS42S81600B, IS42S16800B ClOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...

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... IS42S81600B, IS42S16800B ClOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/DQML DQMH A0-A9, A11 COLUMN m ( A10 BA0, BA1 BANK DQ Notes: 1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled. ...

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... IS42S81600B, IS42S16800B PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks.The bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE rp command is issued. Input A10 determines whether one or ...

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... IS42S81600B, IS42S16800B POWER-DOWN MODE CYClE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/DQML DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles All banks idle, enter Precharge all active banks power-down mode Integrated Silicon Solution, Inc. — ...

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... IS42S81600B, IS42S16800B BURST READ/SINGlE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access ...

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... IS42S81600B, IS42S16800B WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t is met, where t begins when the READ to bank m is dpl registered ...

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... IS42S81600B, IS42S16800B SINGlE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) X16: A9 and A11 = " ...

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... IS42S81600B, IS42S16800B READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD ...

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... IS42S81600B, IS42S16800B SINGlE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC ...

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... IS42S81600B, IS42S16800B READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD ...

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... IS42S81600B, IS42S16800B SINGlE WRITE WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM/DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) X16: A9 and A11 = " ...

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... IS42S81600B, IS42S16800B SINGlE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW DISABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC ...

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... IS42S81600B, IS42S16800B WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/DQML DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 4 2) X16: A9 and A11 = " ...

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... IS42S81600B, IS42S16800B WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK ...

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... IS42S81600B, IS42S16800B ORDERING INFORMATION - V Commercial Range: 0°C to 70°C Frequency Speed (ns) Order Part No. 167 MHz 6 IS42S81600B-6T 143 MHz 7 IS42S81600B-7T Frequency Speed (ns) Order Part No. 167 MHz 6 IS42S16800B-6T 143 MHz 7 IS42S16800B-7T ORDERING INFORMATION - V Industrial Range: -40°C to 85°C Frequency Speed (ns) Order Part No. ...

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... Frequency Speed (ns) Order Part No. 143 MHz 7 IS42S81600B-7TLI Frequency Speed (ns) Order Part No. 167 MHz 6 IS42S16800B-6TI IS42S16800B-6TLI 143 MHz 7 IS42S16800B-7TLI Please contact Product Manager for Leaded parts support. Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 12/06/07 = 3.3V DD Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free ...

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... C 0.12 0.21 D 22.02 22.42 E1 10.03 10.29 E 11.56 11.96 e 0.80 BSC L 0.40 0.60 L1 — — — ZD 0.71 REF 0° 8° Integrated Silicon Solution, Inc. Rev. D 03/13/07 N/2 Inches Min Max Symbol Ref. Std. No. Leads (N) 0.047 0.002 0.006 — 0.012 0.018 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 — ...