m58lt256jsb STMicroelectronics, m58lt256jsb Datasheet - Page 41

• Manufacturer Part Number: m58lt256jsb
• Description: 256 Mbit 16 Mb 16, Multiple Bank, Multilevel, Burst 1.8 V Supply, Secure Flash Memories
• Manufacturer: STMicroelectronics

M58LT256JST, M58LT256JSB
Table 11.
1. The combination X latency=2, Data held for two clock cycles and Wait active one data cycle before the
CR13-CR11
CR5-CR4
CR2-CR0
WAIT state is not supported.
CR15
CR14
CR10
CR9
CR8
CR7
CR6
CR3
Bit
Configuration Register
Read select
Reserved
Wait polarity
Data output configuration
Wait configuration
Burst type
Valid clock edge
Reserved
Wrap burst
Burst length
X latency
Description
0
1
010
011
100
101
110
111
Other configurations reserved
0
1
0
1
0
1
0
1
0
1
0
1
001
010
111
Value
Synchronous read
Asynchronous read (default at power-on)
2 clock latency
3 clock latency
4 clock latency
5 clock latency
6 clock latency
7 clock latency (default)
WAIT is active Low
WAIT is active High (default)
Data held for one clock cycle
Data held for two clock cycles (default)
WAIT is active during WAIT state
WAIT is active one data cycle before WAIT
state
Reserved
Sequential (default)
Falling Clock edge
Rising Clock edge (default)
Wrap
No wrap (default)
4 words
8 words
Continuous (default)
(1)
(default)
(1)
Description
Configuration Register
(1)
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