hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 7

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hyb18t512160bf-5

Manufacturer Part Number
hyb18t512160bf-5
Description
240-pin Unbuffered Ddr2 Sdram Modules
Manufacturer
Infineon Technologies Corporation
Datasheet
1.2
The INFINEON HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A module family are unbuffered DIMM modules
“UDIMMs” with 30,0 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in
16M × 64 (128MB), 32M × 64 (256MB), 64M × 64 (512MB) and as ECC modules in 32M × 72 (256MB), 64M × 72
(512MB) organization and density, intended for mounting into 240-pin connector sockets.
The memory array is designed with 256-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E
device using the 2-pin I
protected; the second 128 bytes are available to the customer.
Table 3
Product Type
PC2–6400
HYS64T32001HU–2.5–A 256MB 1Rx8 PC2–6400U–666–12–D0
HYS64T64020HU–2.5–A 512MB 2Rx8 PC2–6400U–666–12–E0
PC2–5300
HYS64T32001HU–3–A
HYS64T64020HU-3-A
HYS72T32000HU–3–A
HYS72T64020HU-3-A
HYS64T32001HU-3S-A
HYS64T64020HU-3S-A
HYS72T32000HU–3S–A
HYS72T64020HU-3S-A
PC2–4200
HYS64T16000HU–3.7–A 128MB 1Rx16 PC2–4200U–444–11–C1 1 Rank, Non-ECC
HYS64T32001HU–3.7–A 256MB 1Rx8 PC2–4200U–444–11–A1
HYS72T32000HU–3.7–A 256MB 1Rx8 PC2–4200U–444–11–A1
PC2–3200
HYS64T16000HU–5–A
HYS64T32001HU–5–A
HYS72T32000HU–5–A
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS64T16000HU–3.7–A, indicating
2) The Compliance Code is printed on the module label and describes the speed grade, for example “
Data Sheet
Rev. “A” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see
Chapter 6
11–C1
Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4
using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card “C”.
”, where 4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means
Description
Ordering Information for RoHS Compliant Products
of this data sheet.
1)
2
C protocol. The first 128 bytes are programmed with configuration data and are write
Compliance Code
256MB 1Rx8 PC2–5300U–444–12–D0
512MB 2Rx8 PC2–5300U–444–12–E0
256MB 1Rx8 PC2–5300U–444–12–F0
512MB 2Rx8 PC2–5300U–444–12–G0 2 Ranks, ECC
256MB 1Rx8 PC2–5300U–444–12–D0
512MB 2Rx8 PC2–5300U–555–12–E0
256MB 1Rx8 PC2–5300U–555–12–F0
512MB 2Rx8 PC2–5300U–555–12–G0 2 Ranks, ECC
128MB 1Rx16 PC2–3200U–333–11–C1 1 Rank, Non-ECC
256MB 1Rx8 PC2–3200U–333–11–A1
256MB 1Rx8 PC2–3200U–333–11–A1
2)
7
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
Unbuffered DDR2 SDRAM Modules
Description
1 Rank, Non-ECC
2 Ranks, Non-ECC 256 Mbit (x8)
1 Rank, Non-ECC
2 Ranks, Non-ECC 256 Mbit (x8)
1 Rank, ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC 256 Mbit (x8)
1 Rank, ECC
1 Rank, Non-ECC
1 Rank, ECC
1 Rank, Non-ECC
1 Rank, ECC
02182004-DHQB-4RRW
SDRAM Technology
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x16)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x16)
256 Mbit (x8)
256 Mbit (x8)
PC2–4200U–444–
Rev. 1.3, 2005-09
Overview
2
PROM

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