hyb18t512161bf-33 Infineon Technologies Corporation, hyb18t512161bf-33 Datasheet
hyb18t512161bf-33
Related parts for hyb18t512161bf-33
hyb18t512161bf-33 Summary of contents
Page 1
512-Mbit x16 DDR2 SDRAM ...
Page 2
Edition 2005-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
Page 3
... HYB18T512161BF Revision History: 2005-08, Rev. 1.1 Page Subjects (major changes since last revision) All added speed sort -33 added note 2 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
Page 4
... Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.26.1 No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.26.2 Deselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.27 Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.28 Asynchronous CKE LOW Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.29 DLL off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.29.1 DLL off Frequency Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 HYB18T512161BF–22/25/28/33 Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 5
... Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7.1 Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7.2 AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.7.3 ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6 Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I 6.1 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DD 6.1.1 On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.1 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.2 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM 5 Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 6
... Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank Figure 47 Write with Auto-Precharge Example 1 ( Figure 48 Write with Auto-Precharge Example 2 (WR + Figure 49 Auto Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM 16 I/O 4 Internal Memory Banks Limit Limit HYB18T512161BF–22/25/28/33 List of Figures t Limit Limit RAS Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 7
... Figure 62 AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 63 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . 76 Figure 64 Package Outline P-TFBGA-84 (top view Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM 7 List of Figures WTR Rev. 1.1, 2005-08 ...
Page 8
... DD I Table 41 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 42 Measurement Test Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DD Table 43 ODT current per terminated input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 44 Package thermal characteristics Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM ) . . . . . . . . . . . . . . . . . List of Tables Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 9
... Average Refresh Period 7 than 85 °C, 3.9 s between 85 °C and 95 °C • Full Strength and reduced Strength (60%) Data- Output Drivers • 2kB page size • Packages: P-TFBGA-84 for 16 components • RoHS Compliant Products Org. Clock (MHz) Package 16 450/400/350/300 P-TFBGA-84 9 HYB18T512161BF T lower CASE 1) Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 10
... The functionality specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in P-TFBGA package. Chapter 8 of this data sheet 10 HYB18T512161BF–22/25/28/33 Overview described and the Rev. 1.1, 2005-08 05102005-C5U8-7TLE timing ...
Page 11
... SSTL Bank Address Bus 1:0 SSTL – SSTL Address Signal 12:0,Address Signal 10/Autoprecharge SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL 11 HYB18T512161BF–22/25/28/33 Pin Configuration and Block Diagrams 2. The abbreviations used in the Pin#/Buffer Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 12
... SSTL Data Mask Lower Byte – I/O Driver Power Supply – Power Supply – Power Supply – Power Supply – I/O Reference Voltage – I/O Driver Power Supply – Power Supply – Power Supply 12 HYB18T512161BF–22/25/28/33 Pin Configuration and Block Diagrams Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 13
... Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM Buffer Function Type – Power Supply – Power Supply – Power Supply – Not Connected SSTL On-Die Termination Control 13 HYB18T512161BF–22/25/28/33 Pin Configuration and Block Diagrams Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 14
... DQ[15: and V are power and ground for the DLL. DDL DDSL They are isolated on the device from V and V SSQ. Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM Pin Configuration and Block Diagrams , DDQ SS 14 HYB18T512161BF–22/25/28/33 Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 15
... Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Referred to as ’colbits’ 2) Referred to as ’org’ colbits 3) PageSize = 2 org/8 [Bytes Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM Pin Configuration and Block Diagrams 32-Mbit x 16 BA[1:0] 4 A10 / AP A[12:0] A[9: 2048 (2K) ...
Page 16
... Double-Data-Rate-Two SDRAM 16 I/O 4 Internal Memory Banks device; it does not represent an actual circuit implementation. 3. LDM, UDM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional LDQS and UDQS signals. 16 HYB18T512161BF–22/25/28/33 Pin Configuration and Block Diagrams Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 17
... In particular situations involving more than one bank, enabling / disabling on-die termination, Power-Down entry / exit, timing restrictions during state transitions - among other things - are not captured in full detail. Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM 17 Functional Description Rev. 1.1, 2005-08 ...
Page 18
... OCD calibration or V – select the OCD default. Issue the final EMRS(1) DDL. V – command to exit OCD calibration mode and set the DDQ. V & necessary operating parameters. TT 13. The DDR2 SDRAM is now ready for normal operation. 18 HYB18T512161BF–22/25/28/33 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 19
... Reset do not affect array contents, which means reinstallation including those can be executed any time after power-up without affecting array contents. 19 HYB18T512161BF–22/25/28/33 Functional Description ). MRS, EMRS and DLL MRD Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 20
... Power- Down mode, where the DLL is disabled. Address bit required to A13 and all “higher” address bits have to be set to 0 for MRD compatibility with other DDR2 memory products with higher memory densities. 20 HYB18T512161BF–22/25/28/33 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 21
... A13, Address bit 13 PD, Fast exit PD, Slow exit DLL, No DLL, Yes TM, Normal Mode TM, Vendor specific test mode CL, reserved HYB18T512161BF–22/25/28/33 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 22
... DDR2 memory products with higher memory densities. Refer to Extended Mode Register Definition. BA2, Bank Address BA1, Bank Address BA0, Bank Address 22 HYB18T512161BF–22/25/28/33 Functional Description (ns). The mode register must be programmed to CK and WR is determined by CK.MAX MAX Rev ...
Page 23
... OCD, OCD calibration default RTT, (ODT disabled) B RTT, 75 Ohm B RTT, 150 Ohm B RTT, 50 Ohm B DIC, Full (Driver Size = 100%) DIC, Reduced DLL, Enable DLL, Disable 23 HYB18T512161BF–22/25/28/33 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 24
... Strobe Function Matrix RDQS/DM RDQS DQS DM Hi-Z DQS DM Hi-Z DQS RDQS RDQS DQS RDQS Hi-Z DQS 24 HYB18T512161BF–22/25/28/33 Functional Description parameters. AC DQSCK I DD Signaling DQS DQS differential DQS signals Hi-Z single-ended DQS signals DQS differential DQS signals ...
Page 25
... A[13:0], Address bits A7, disable 2)3) A7, enable A[6:0], Address bits PASR0, Full Array PASR1, Half Array (BA[1:0]=00, 01) PASR2, Quarter Array (BA[1:0]=00) PASR3, Not defined PASR4, 3/4 array (BA[1:0]=01, 10, 11) PASR5, Half array (BA[1:0]=10, 11) PASR6, Quarter array (BA[1:0]=11) PASR7, Not defined 25 HYB18T512161BF–22/25/28/33 Functional Description ) must be satisfied to complete the write ) B Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 26
... Case initialization. The EMRS(3) is written by asserting low on CS, RAS, CAS, WE, BA2 and high on BA0 and BA1, while controlling the state of the address pins. BA2, Bank Address BA1, Bank Address BA0, Bank Address A[13:0], Address bits 26 HYB18T512161BF–22/25/28/33 Functional Description ) B Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 27
... OCD Impedance Adjustment Flow Chart Note: MR should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM command being issued. MRS should be set before entering OCD impedance adjustment and On Die Termination (ODT) should be carefully controlled depending on system environment ...
Page 28
... Pull-up driver strength NOP (no operation) Increase by 1 step Decrease by 1 step NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step 28 HYB18T512161BF–22/25/28/33 Functional Description should be met as shown Input data pattern for adjustment, DT[0:3] Pull-down driver strength NOP (no operation) ...
Page 29
... Both Drive(1) and Drive(0) are used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are Figure 7 Timing Diagram Drive Mode Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM Operation Pull-up driver strength Decrease by 1 step Illegal ...
Page 30
... The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS(1) for the device organization Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM only when enabled in the EMRS(1) by address bit A10 = 0. The ODT feature is designed to improve signal integrity ...
Page 31
... LDQS LDQS UDQS UDQS LDM UDM Note don’t care bit set to low bit set to high Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM EMRS(1) Address Bit A10 HYB18T512161BF–22/25/28/33 Functional Description EMRS(1) Address Bit A11 X X Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 32
... ODT turn on time max. ( the ODT resistance is fully on. Both are measured from t 3. ODT turn off time min. ( starts to turn off the ODT resistance.ODT turn off time max. ( impedance. Both are measured from 32 HYB18T512161BF–22/25/28/33 Functional Description AOND AOFD t AON ...
Page 33
... When entering the Power Down Modes “Slow Exit” Active Power Down and Precharge Power Down two additional t t timing parameters ( and ANPD AXPD Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM ) define if synchronous or asynchronous ODT timings have to be applied. 33 HYB18T512161BF–22/25/28/33 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 34
... ODT is turned on or off before entering these power-down modes, synchronous timing parameters Figure 11 ODT Mode Entry Timing Diagram Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM t is satisfied can be ANPD.MIN asynchronous timing parameters apply. 34 HYB18T512161BF–22/25/28/33 Functional Description t applied not ANPD.MIN Rev. 1.1, 2005-08 05102005-C5U8-7TLE satisfied, ...
Page 35
... ODT is turned on or off after exiting these power- down modes, synchronous timing parameters can be Figure 12 ODT Mode Exit Timing Diagram Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM t is satisfied applied. If AXPD.MIN parameters apply. 35 HYB18T512161BF–22/25/28/33 Functional Description t is not satisfied, asynchronous timing AXPD.MIN Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 36
... The minimum time interval between successive Bank Activate commands to the same bank is determined by between Bank Active commands to different banks RRD 36 HYB18T512161BF–22/25/28/33 Functional Description is satisfied. Additive latencies and t . The minimum time interval RC Rev. 1.1, 2005-08 05102005-C5U8-7TLE t ...
Page 37
... Figure 14 Read Timing Example Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM during the Read or Write Command (CA[11, 9:0]). The second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence ...
Page 38
... RCD user chooses to issue a Read command after the t RCD.MIN CL and ( (RL - and ( (RL - HYB18T512161BF–22/25/28/33 Functional Description t RCD.MIN period, the Read Latency is also defined as Rev. 1.1, 2005-08 05102005-C5U8-7TLE , then AL ...
Page 39
... Write to Read Timing Example: Write followed by a read to the same bank Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM : ( (RL - WTR 39 HYB18T512161BF–22/25/28/33 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 40
... CA11); Page Size = 1 kByte; Page Length = 2048 64Mb x 8 organization (CA[9:0]); Page Size = 1 Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM the MR. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MR. Seamless burst read or write operations are supported ...
Page 41
... Basic Read Timing Diagram Figure 21 Read Operation Example ( Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner ...
Page 42
... (RL- The minimum time from the read command to the write command is defined by a read-to-write turn-around time, which is BL clocks. Figure 24 Seamless Read Operation Example Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM 42 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 43
... (non interrupting) The seamless, non interrupting 8-bit read operation is supported by enabling a read command at every BL/2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM 43 Functional Description Rev. 1.1, 2005-08 ...
Page 44
... Basic Write Timing Figure 27 Write Operation Example ( 3 Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM successive edges of the DQS until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete ...
Page 45
... Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM WTR t expressed in clock cycles. The WTR 45 HYB18T512161BF–22/25/28/33 Functional Description t , where WTR t is not a write recovery time ( WTR Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 46
... non interrupting The seamless non interrupting 8-bit write operation is supported by enabling a write command at every BL/2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM 46 Functional Description Rev. 1.1, 2005-08 ...
Page 47
... For function is disabled, when RDQS / RDQS are enabled by EMRS(1 DQS DQS HYB18T512161BF–22/25/28/33 Functional Description 8 components the PST don' t car e Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 48
... Read Interrupt Timing Example Figure 35 Write Interrupt Timing Example Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM 6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted. 7. Read burst interruption is allowed by a Read with Auto-Precharge command ...
Page 49
... The RAS precharge time ( from the clock at which the precharge begins. 2. The RAS cycle time ( activation has been satisfied CKs RTP 49 HYB18T512161BF–22/25/28/33 Functional Description Precharge Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only all banks - clocks for operating ...
Page 50
... Figure 37 Read Operation Followed by Precharge Example ( 3 Figure 38 Read Operation Followed by Precharge Example ( 3 Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM t 2 CKs RTP t 2 CKs RTP 50 HYB18T512161BF–22/25/28/33 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 51
... RTP t 2 CKs RTP to the Precharge command. No Precharge command should be issued prior to the SDRAM does not support any burst interrupt by a Precharge command. parameter programmed value WR in the MR. 51 HYB18T512161BF–22/25/28/33 Functional Description t delay, as DDR2 analog timing WR (see Chapter 5.7) ...
Page 52
... Figure 41 Write followed by Precharge Example ( Figure 42 Write followed by Precharge Example ( Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM 52 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 53
... The RAS precharge time ( RTP RP from the clock at which the Auto-Precharge begins. 2. The RAS cycle time ( activation has been satisfied. 53 HYB18T512161BF–22/25/28/33 Functional Description For the time from Read RTP ...
Page 54
... ( 3 Figure 44 Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank ( ( 3 Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM t 2 CKs RTP t 2 CKs RTP 54 HYB18T512161BF–22/25/28/33 Functional Description RAS Rev. 1.1, 2005-08 05102005-C5U8-7TLE Limit) Limit) ...
Page 55
... Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank ( 3 Figure 46 Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank ( 4 Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM t 2 CKs RTP t 3 CKs RTP 55 HYB18T512161BF–22/25/28/33 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 56
... MRS mode register. As long as the analog WR can be programmed between 2 and 6 clock cycles. Minimum Write to Activate command spacing to the same bank = Limit HYB18T512161BF–22/25/28/33 Functional Description t ) has been satisfied from the previous bank RC t timing parameter is not violated ...
Page 57
... For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge-all, issued to that bank. The precharge period is satisfied after command issued to that bank Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM Minimum Delay between “From Command” to “To Command” ...
Page 58
... A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command HYB18T512161BF–22/25/28/33 Functional Description Unit t t WTR CK ...
Page 59
... Self Refresh mode is . The user may change the CKE external clock frequency or halt the external clock one Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self-Refresh operation. ...
Page 60
... CKE LOW and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are “Don’t Care”. Power-down duration is limited by 9 times 60 HYB18T512161BF–22/25/28/33 Functional Description has to be satisfied for any command except a V must be ...
Page 61
... Active Power-Down Mode Entry and Exit after an Activate Command Note: Active Power-Down mode exit timing state in the MR, address bit A12. Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress ...
Page 62
... Active Power-Down Mode Entry and Exit Example after a Write Command WTR Note: Active Power-Down mode exit timing state in the MR, address bit A12. Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM (“fast exit” (“slow exit”) depends on the programmed XARD XARDS t t (“ ...
Page 63
... Precharge Power Down Mode Entry and Exit Note: "Precharge" may be an external command or an internal precharge following Write with AP. Figure 56 Auto-Refresh command to Power-Down entry Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM t t (“fast exit”) or (“slow exit”) depends on the programmed ...
Page 64
... Figure 57 MRS, EMRS command to Power-Down entry Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM 64 Functional Description Rev. 1.1, 2005-08 05102005-C5U8-7TLE ...
Page 65
... LOW state. After a minimum of two clock Figure 58 Input Frequency Change Example during Precharge Power-Down mode Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM registered when CS is LOW with RAS, CAS, and WE held HIGH at the rising edge of the clock Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle ...
Page 66
... DRAM is not guaranteed to preserve the contents of the memory array. If this event Figure 59 Asynchronous Low Reset Event Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM occurs, the memory controller must satisfy a time delay before turning off the clocks. Stable clocks must ...
Page 67
... DLL off Frequency Definition Speed Grade Parameter Clock Frequency @ Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM –22 –25 Symbol Min. Max. Min 250 HYB18T512161BF–22/25/28/33 Functional Description –28 –33 Max. Min. Max. Min. Max. 250 50 250 50 250 Rev. 1.1, 2005-08 05102005-C5U8-7TLE Unit — ...
Page 68
... Chapter 3.21 Chapter 3.28 68 HYB18T512161BF–22/25/28/33 Truth Tables A[13:11] A10 A[9:0] BA1 BA OP Code Row Address BA Column L Column BA Column H ...
Page 69
... Refer to the Command Truth Table )” in Self Refresh and Power Down. However ODT must be driven V REF + CKE IH (200 clocks) is satisfied. t XSRD Chapter 3.25 69 HYB18T512161BF–22/25/28/33 2)3) 2) Action (N) Maintain Power-Down Maintain Self Refresh Entry Self Refresh Entry . and Chapter 3.24.2 for a detailed list of restrictions. DM DQs L Valid H X Rev ...
Page 70
... Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM Rating temperature range, the High Temperature Self Refresh has to be ...
Page 71
... DD Supply Voltage for DLL V DDDL Supply Voltage for Output V DDQ Input Reference Voltage V REF Termination Voltage HYB18T512161BF–[25/28/33] tracks with tracks with DDQ DD DDDL together. 3) HYB18T512161BF–22 4) The value of may be selected by the user to provide optimum noise margin in the system. Typically the value of ...
Page 72
... IL(ac).MAX 3) AC timings are referenced with input waveforms switching from on the negative transitions. Figure 60 Single-ended AC Input Test Conditions Diagram Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM relative to the rising or falling edges of DQS crossing differential mode, these timing relationships V REF are measured relative to the crosspoint of DQS and its complement, DQS ...
Page 73
... the transmitting device and V DDQ of the transmitting device and V DDQ 2) Nominal Low Nominal 3) (18.75 Ohms) (18 ohms) –10.7 –11.4 –16.0 –16.5 –21.0 –21.2 T CASE 73 HYB18T512161BF–22/25/28/33 Electrical Characteristics Max. Unit + 0.3 — V DDQ + 0.6 — V DDQ + 0 DDQ 0.5 + 0.175 V V DDQ 0.5 + 0.125 V V DDQ ...
Page 74
... The driver characteristics evaluation conditions are Nominal 25 ° The driver characteristics evaluation conditions are Nominal Maximum 0 °C ( Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM 1) 2) Nominal Low Nominal (18.75 Ohms) (18 ohms) 10.7 11.5 16.0 16.6 21.0 21.6 T CASE 74 HYB18T512161BF–22/25/28/33 Electrical Characteristics 3) 2) Nominal High Nominal (17.25 Ohms) Maximum (15 Ohms) 11.8 13.3 17.4 20.0 23.0 27 1.7 V, any process T V ...
Page 75
... Input capacitance, all other input-only pins CDI Input capacitance delta, all other input-only pins CIO Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS CDIO Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM Electrical Characteristics Min. Max. 1.0 2.0 — 0.25 1.0 1.75 — ...
Page 76
... Maximum overshoot area above Maximum undershoot area below Figure 63 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM – –22 0.9 0.23 V DDQ 0.23 V SSQ 76 HYB18T512161BF–22/25/28/33 Electrical Characteristics –25 –28 –33 0.5 0.5 0.5 0.5 0.5 0.5 0.80 0.80 0.80 0.80 0.80 0.80 –25 –28 –33 0.9 0.9 ...
Page 77
... RC 15 — 15 — RCD 15 — 15 — RP stabilizes. During the period before V REF . See section 8 for the reference load for timing measurements HYB18T512161BF–22/25/28/33 Electrical Characteristics –28 –33 Unit Note Min. Max. Min. Max. 3. 3. ...
Page 78
... Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from DQS low-impedance from Mode register set command cycle time Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM Symbol –22 –25 Min. Max. Min. ...
Page 79
... XP +10 — RFC XSNR 200 — t XSRD stabilizes. During the period before V REF . See Chapter 5 for the reference load for timing measurements HYB18T512161BF–22/25/28/33 Electrical Characteristics –25 Unit Notes 1)2)3)4) Min. Max. 5) –t — QHS — 600 ps 13)14) — ...
Page 80
... DH 400 t DH1 0.35 t DIPW –550 t DQSCK 0.35 t DQSL,H — t DQSQ WL – 0. 0.25 WL – 0. 0.25 t DQSS 80 HYB18T512161BF–22/25/28/33 Electrical Characteristics and ). t CH transitions occur in the same access time windows as timing parameter, where For each of the terms, if not DAL RP CK 200 z. can be used. In “low active power-down ...
Page 81
... Write recovery time for write with Auto- Precharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Data Sheet HYB18T512161BF–22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM Symbol –28 –33 Min. Max. Min. 400 – ...
Page 82
... LZ, RPRE HZ LZ parameter is not a device limit. The device operates with a greater value for this parameter, refers to the application clock period. WR refers to the has to be satisfied. t XARDS 82 HYB18T512161BF–22/25/28/33 Electrical Characteristics –33 Max. Min. Max. — 2 — — +10 — t RFC — ...
Page 83
... Max AC.MIN AC.MAX + AC.MIN 2.5 2 AC.MIN AC.MAX + 2 ns 2.5 t AC.MIN — 8 — AOND . t AOFD 83 HYB18T512161BF–22/25/28/33 Electrical Characteristics Unit Note 0 AC.MAX 0 AC.MAX Rev. 1.1, 2005-08 05102005-C5U8-7TLE 1) 2) ...
Page 84
... CKE is HIGH HIGH between RAS.MAX(IDD) RP RP(IDD mA. OUT interval, CKE is HIGH HIGH between RFC RFC(IDD 7.8 s interval, CKE is LOW and CS is HIGH REFI 84 HYB18T512161BF–22/25/28/33 Specifications and Conditions Symbol Note RCD RCD(IDD ...
Page 85
... OUT (IDD CKE is HIGH HIGH between valid commands. RRD(IDD) 0 current measurements are defined in chapter 7 IL(ac).MAX V IH(ac).MIN REF DDQ 85 HYB18T512161BF–22/25/28/33 Specifications and Conditions Symbol Note RCD(IDD) CK(IDD) CK Rev. 1.1, 2005-08 05102005-C5U8-7TLE 1)2)3)4) DD6 5)6) 1)2)3)4) DD7 ...
Page 86
... HYB18T512161BF–22/25/28/33 Specifications and Conditions -33 Unit Note Max. tbd mA 16 tbd mA 16 tbd mA tbd mA tbd mA 1) tbd mA 2) tbd ...
Page 87
... Double-Data-Rate-Two SDRAM Symbol CL IDD t CKIDD t RCD.IDD t RC.IDD t RRD.IDD t RAS.MIN.IDD t RAS.MAX.IDD t RP.IDD CASE RFC.IDD CASE REFI 87 HYB18T512161BF–22/25/28/33 Specifications and Conditions –22 –25 –28 –33 Unit Notes 2.5 2.5 2.5 2 ...
Page 88
... Note: For power consumption calculations the ODT duty cycle has to be taken into account Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM Table 43 EMRS(1) State DDQ ODTO current DDQ ODTT HYB18T512161BF–22/25/28/33 Specifications and Conditions Min. Typ. Max. Unit 5 6 7.5 mA/DQ 2.5 3 3.75 mA/DQ 7.5 9 11.25 mA/DQ 10 ...
Page 89
... Junction to Ambient thermal resistance. The value has been obtained by simulation using the conditions stated in the JEDEC JESD-51 standard. 2) Junction to Case thermal resistance. The value has been obtained by simulation. Data Sheet 512-Mbit Double-Data-Rate-Two SDRAM 2s0p 1 m/s 3 m HYB18T512161BF–22/25/28/33 Package Theta_jC 1 m Rev. 1.1, 2005-08 05102005-C5U8-7TLE 2) ...
Page 90
Published by Infineon Technologies AG ...