dsm2180f3 STMicroelectronics, dsm2180f3 Datasheet - Page 10

• Manufacturer Part Number: dsm2180f3
• Description: Dsm Digital Signal Processor System Memory For Analog Devices Adsp-218x Family 5v Supply
• Manufacturer: STMicroelectronics

DSM2180F3
Table 3. Pin Description
10/63
ADIO0-15
CNTL0
CNTL1
CNTL2
Reset
PA0-7
PB0-7
PC0-7
PD0-2
V
GND
Pin Name
CC
In
In
In
In
In
I/O
I/O
I/O
I/O
Type
Sixteen address inputs from the DSP.
Active low write strobe input (WR) from the DSP
Active low read strobe input (RD) from the DSP.
Active low Byte Memory Select (BMS) signal from the DSP.
Active low reset input from system. Resets DSM I/O Ports, Page Register contents, and other
DSM configuration registers. Must be logic Low at Power-up.
Eight data bus signals connected to DSP pins D8 - D15.
Eight configurable Port B signals with the following functions:
Note: Each of the four Port B signals PB0-PB3 may be configured at run-time as either standard
Eight configurable Port C signals with the following functions:
Note 2: Port C pin PC7 input (or any PLD input pin) can be connected to DSP D19 output which
Note 3: When used as general I/O, each of the eight Port C signals may be configured at run-time
Note 4: The JTAG ISP pins may be multiplexed with other I/O functions.
Three configurable Port D signals with the following functions:
Note 1: It is recommended to connect Port D pin PD0 input to DSP IOMS output which is the
Note 2: It is recommended to connect Port D pin PD1 input to DSP DMS output which is the active
Note 3: It is recommended to connect Port D pin PD2 input to DSP PWDACK output if the DSP
Supply Voltage
Ground pins
Note 1: Port C pin PC2 input (or any PLD input pin) can be connected to DSP D18 output which
1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers.
2. CPLD Output Macrocell (McellBC0-7) output.
3. Input to the PLDs (Input Macrocells).
4. Pins PC0, PC1, PC5, and PC6 can optionally form the JTAG IEEE-1149.1 ISP serial
5. Pins PC3 and PC4 can optionally form the enhanced JTAG signals TSTAT and TERR
6. Pin PC3 can optionally be configured as the Ready/Busy output to indicate Flash memory
1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers.
2. CPLD Output Macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs (Input Macrocells).
1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers.
2. Input to the PLDs (no associated Input Macrocells, routes directly into PLDs).
3. CPLD output (External Chip Select). Does not consume Output Macrocells.
4. Pin PD1 can optionally be configured as CLKIN, a common clock input to PLD.
5. Pin PD2 can optionally be configured as CSI, an active low Chip Select Input to select Flash
interface as signals TMS, TCK, TDI, and TDO respectively.
respectively. Reduces ISP programming time by up to 30% when used in addition to the
standard four JTAG signals: TDI, TDO, TMS, TCK.
programming status during parallel programming. May be polled by DSP or used as DSP
interrupt to indicate when Flash memory byte programming or erase operations are
complete.
memory. Flash memory is disabled to conserve more power when CSI is logic high. Can
connect CSI to ADSP-218X PWDACK output signal.
CMOS or for high slew rate. Each of the four Port B signals PB3-PB7 may be configured at
run-time as either standard CMOS or Open Drain Outputs.
functions as DSP address A16 in DSP Full Memory Mode. See Figure 6.
functions as DSP address A17 in DSP Full Memory Mode. See Figure 6.
active low I/O Memory Select strobe. See Figure 6.
low Data Memory Select strobe. See Figure 6.
Power Down mode is used. See Figure 6.
as either standard CMOS or Open Drain Outputs.
Description