dsm2180f3 STMicroelectronics, dsm2180f3 Datasheet - Page 21

• Manufacturer Part Number: dsm2180f3
• Description: Dsm Digital Signal Processor System Memory For Analog Devices Adsp-218x Family 5v Supply
• Manufacturer: STMicroelectronics

section entitled “Programming Flash Memory”, on
page 21, for details.
Data Polling Flag (DQ7). When erasing or pro-
gramming in Flash memory, the Data Polling Flag
(DQ7) bit outputs the complement of the bit being
entered for programming/writing on the Data Poll-
ing Flag (DQ7) bit. Once the Program instruction
sequence or the write operation is completed, the
true logic value is read on the Data Polling Flag
(DQ7) bit (in a read operation).
Flash memory instruction features:
Toggle Flag (DQ6). The device offers another
way for determining when the Flash memory Pro-
gram cycle is completed. During the internal write
operation and when the Sector Select FS0-FS7 is
true, the Toggle Flag (DQ6) bit toggles from 0 to 1
and 1 to 0 on subsequent attempts to read any
byte of the memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-7 is
the addressed memory byte. The device is now
accessible for a new read or write operation. The
cycle is finished when two successive reads yield
the same output data. Flash memory specific fea-
tures:
Data Polling is effective after the fourth Write
pulse (for a Program instruction sequence) or
after the sixth Write pulse (for an Erase
instruction sequence). It must be performed at
the address being programmed or at an address
within the Flash memory sector being erased.
During an Erase cycle, the Data Polling Flag
(DQ7) bit outputs a 0. After completion of the
cycle, the Data Polling Flag (DQ7) bit outputs
the last bit programmed (it is a 1 after erasing).
If the byte to be programmed is in a protected
Flash memory sector, the instruction sequence
is ignored.
If all the Flash memory sectors to be erased are
protected, the Data Polling Flag (DQ7) bit is
reset to 0 for about 100 µs, and then returns to
the previous addressed byte. No erasure is
performed.
The Toggle Flag (DQ6) bit is effective after the
fourth write operation (for a Program instruction
sequence) or after the sixth write operation (for
an Erase instruction sequence).
If the byte to be programmed belongs to a
protected Flash memory sector, the instruction
sequence is ignored.
If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag (DQ6) bit
Error Flag (DQ5). During a normal Program or
Erase cycle, the Error Flag (DQ5) bit is to 0. This
bit is set to 1 when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag (DQ5) bit indicates the attempt to program
a Flash memory bit from the programmed state, 0,
to the erased state, 1, which is not valid. The Error
Flag (DQ5) bit may also indicate a Time-out condi-
tion while attempting to program a byte.
In case of an error in a Flash memory Sector Erase
or Byte Program cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag (DQ5) bit is reset after a Reset
Flash instruction sequence.
Erase Time-out Flag (DQ3). The Erase Time-
out Flag (DQ3) bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
struction sequence bytes. The Erase Time-out
Flag (DQ3) bit is reset to 0 after a Sector Erase cy-
cle for a time period of 100 µs + 20% unless an ad-
ditional Sector Erase instruction sequence is
decoded. After this time period, or when the addi-
tional Sector Erase instruction sequence is decod-
ed, the Erase Time-out Flag (DQ3) bit is set to 1.
Programming Flash Memory
When a byte of Flash memory is programmed, in-
dividual bits are programmed to logic 0. You can-
not program a bit in Flash memory to a logic 1
once it has been programmed to a logic 0. A bit
must be erased to logic 1, and programmed to log-
ic 0. That means Flash memory must be erased
prior to being programmed. A byte of Flash mem-
ory is erased to all 1s (FFh). The DSP may erase
the entire Flash memory array all at once or indi-
vidual sector-by-sector, but not byte-by-byte.
However, the DSP may program Flash memory
byte-by-byte.
The Flash memory requires the DSP to send an in-
struction sequence to program a byte or to erase
sectors (see Table 5).
Once the DSP issues a Flash memory Program or
Erase instruction sequence, it must check for the
status bits for completion. The embedded algo-
rithms that are invoked inside the device provide
several ways give status to the DSP. Status may
be checked using any of three methods: Data Poll-
ing, Data Toggle, or Ready/Busy (pin PC3).
Data Polling. Polling on the Data Polling Flag
(DQ7) bit is a method of checking whether a Pro-
toggles to 0 for about 100 µs and then returns to
the previous addressed byte.
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