m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 191

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
2.8.6 USB Operation (Endpoints 1 to 4 Receive)
Endpoints 1 to 4 can apply to the isochronous transfer, bulk transfer and interrupt transfer.
The endpoints 1 to 4 respectively have their IN (transmit) FIFOs and OUT (receive) FIFOs.
For using the endpoints 1 to 4 OUT, enable each endpoint OUT FIFO by USB endpoint enable register
(address 028E
FIFO can be set according to the user's system. The buffer size of OUT FIFO can be set to a maximum of
1024 bytes per 64 bytes for one endpoint. When the double buffer mode is enabled, the buffer which has
twice as much as the set size is available for the OUT FIFO. The size and starting location of FIFO, the
double buffer mode enable can be set by USB endpoint x OUT FIFO configuration register (EPxOFC).
When one buffer data is received from the host CPU, the data are written to the endpoint x OUT FIFO and
the number of bytes of receive packet data are stored in USB endpoint x OUT write count register. When
a data receive request from the host CPU occurs while data are already written and OUT FIFO cannot be
received, NAK is automatically transmitted in bulk transfer/interrupt transfer, and an overrun occurs in
isochronous transfer, not receiving the packet data.
The data receive from the host CPU is controlled based on the communication status of endpoints 1 to 4
OUT.
The default of endpoints 1 to 4 is bulk transfer. Each endpoint should be initialized in order to use other
transfer modes.
The receive of endpoints 1 to 4 can select the following functions:
Continuous Receive Mode
AUTO_CLR Function
This function is used for receiving data from the host PC at a higher speed. This mode can be set only
for endpoints 1 to 4 OUT bulk transfer. With continuous transfer mode bit of the EPxOFC being set to
“1”, the continuous receive mode is enabled. The USB function control unit writes the receive data
from the host PC in OUT FIFO sequentially by the maximum packet size that is set in USB endpoint x
OUT MAXP register (EPxOMP). (When the last one packet is smaller than the size set in the
EPxOMP, it is received as a short packet.)
When continuous receive mode is enabled, the buffer size has to be equal to an integral multiple of the
EPxOMP. Further, the user's system has to be comprehended beforehand that the receive data from
the host PC are equal to the buffer size or includes a short packet.
When receive data from OUT FIFO are read, both the OUT_BUF_STS0 and the OUT_BUF_STS1
flags are updated without CLR_OUT_BUF_RDY bit being set to “1”. The AUTO_CLR function is en-
abled by setting AUTO_CLR bit of the EPxOCS to “1”. The AUTO_CLR function is available both in
the continuous receive mode and in the continuous receive mode disable of endpoints 1 to 4 OUT (Not
available with endpoint 0).
16
). The size and the starting location (every 64 bytes) of each endpoint x(x=1 to 4) OUT
page 182 of 354
2. USB function