m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 58

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Operation
Note
2.3.3 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)
In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.3.2.
Operations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figures
2.3.9 and 2.3.10 show the set-up procedures.
Table 2.3.2. Choosed functions
(1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
(2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi
(3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
• Set CLKi and RxDi pins' port direction register to “0”.
RTS function
CLK polarity
Transfer clock
source
and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the
output from the RTSi pin goes to “L” level, which informs the transmission side that the data
receivable status is ready (output the transfer clock from the IC on the transmission side after
checking that the RTS output has gone to “L” level).
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
register is transmitted to the UARTi receive buffer register. The transfer clock stops at “H”
level. At this time, the receive complete flag and the UARTi receive interrupt request bit goes
to “1”.
is read.
Item
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________
O
O
O
_______
Internal clock (f
RTS function enabled
External clock (CLKi pin)
RTS function disabled
Output transmission data at
the falling edge of the
transfer clock
Output transmission data at
the rising edge of the
transfer clock
Set-up
1
/ f
8
/ f
32
)
T
polarity reverse bit
Transfer clock
Continuous receive
mode
Data logic select
function
X
D, R
X
Item
D I/O
2. Clock-Synchronous Serial I/O
O
O
O
O
No reverse
No reverse
LSB first
MSB first
Disabled
Reverse
Reverse
Enabled
Set-up