m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 356
m5m51016btp
Manufacturer Part Number
m5m51016btp
Description
Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M5M51016BTP.pdf
(367 pages)
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M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
4.5 Releasing an External Bus (HOLD input and HLDA output)
The Hold feature is to relinquish the address bus, the data bus, and the control bus on M30245 side in line
with the Hold request from the bus master other than M30245 when the two or more bus masters share the
address bus, the data bus, and the control bus. The Hold feature is effective only in memory expansion
mode and microprocessor mode.
The sequence of using the Hold feature may be:
1. The external bus master turns the input level of the HOLD terminal to “L”.
2. When M30245 becomes ready to relinquish buses, each bus becomes high-impedance state at the
3. The HLDA terminal becomes “L” at the rising edge of the next BCLK.
4. The external bus master uses a bus.
5. When the external bus master finishes using a bus, the external bus master returns the input level of
6. The output from HLDA terminal becomes “H” at the rising edge of the next BCLK.
7. Each bus returns from the high-impedance state to the former state at the falling edge of the next
As given above, each bus invariably gets in the high-impedance state while the HLDA output is “L”. Also,
M30245 does not relinquish buses during a bus cycle. That is, if a Hold request comes in during a bus
cycle, the HLDA output become “L” after that bus cycle finishes.
In the Hold state, the state of each terminal becomes as follows.
• Address bus A
Figure.4.5.1 shows an example of relinquishing external buses.
• Data bus D
• RD, WR, WRL, WRH, BHE
• ALE
• CS0 to CS3
falling edge of BCLK.
the HOLD terminal to “H”.
BCLK.
_____
_______
High-impedance state. The case in which A
space) in microprocessor mode and in memory expansion mode too falls under this category.
High-impedance state. The case in which D
width) in microprocessor mode and in memory expansion mode too falls under this category.
High-impedance state.
An internal clock signal having the same phase as BCLK is output.
High-impedance state. The case in which ports are selected by the chip selection control register too
falls under this category.
__________
__________
_____
__________
_______
________
0
to D
page 347 of 354
0
________
__________
to A
15
19
________
__________
16
8
to D
to A
15
19
__________
are used as ports P1
are used as ports P4
__________
0
0
to P4
to P1
__________
3
7
(64K byte address
(8-bit external bus
4. External Buses
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