el7156 Intersil Corporation, el7156 Datasheet

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el7156

Manufacturer Part Number
el7156
Description
High Performance Pin Driver
Manufacturer
Intersil Corporation
Datasheet

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High Performance Pin Driver
The EL7156 high performance pin driver with three-state is
suited to many ATE and level-shifting applications. The 3.5A
peak drive capability makes this part an excellent choice
when driving high capacitance loads.
The output pin OUT is connected to input pins VH or VL
respectively, depending on the status of the IN pin. When the
OE pin is active low, the output is placed in the three-state
mode. The isolation of the output FETs from the power
supplies enables VH and VL to be set independently,
enabling level-shifting to be implemented. Related to the
EL7155, the EL7156 adds a lower supply pin VS- and makes
VL an isolated and independent input. This feature adds
applications flexibility and improves switching response due
to the increased enhancement of the output FETs.
This pin driver has improved performance over existing pin
drivers. It is specifically designed to operate at voltages
down to 0V across the switch elements while maintaining
good speed and ON-resistance characteristics.
Available in the 8 Ld SOIC and 8 Ld PDIP packages, the
EL7156 is specified for operation over the full -40°C to
+85°C temperature range.
Pinout
GND
VS+
OE
IN
1
2
3
4
(8 LD PDIP, SOIC)
TOP VIEW
O
G
C
L
I
EL7156
®
1
Data Sheet
8
7
6
5
VH
OUT
VL
VS-
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Clocking speeds up to 40MHz
• 15ns t
• 0.5ns rise and fall times mismatch
• 0.5ns t
• 3.5pF typical input capacitance
• 3.5A peak drive
• Low ON-resistance of 3.5Ω
• High capacitive drive capability
• Operates from 4.5V to 16.5V
• Pb-free plus anneal available (RoHS compliant)
Applications
• ATE/burn-in testers
• Level shifting
• IGBT drivers
• CCD drivers
Ordering Information
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
EL7156CN
EL7156CNZ
(Note)
EL7156CS
EL7156CS-T7
EL7156CS-T13
EL7156CSZ
(Note)
EL7156CSZ-T7
(Note)
EL7156CSZ-T13
(Note)
PART NUMBER
All other trademarks mentioned are the property of their respective owners.
R
ON
Copyright © Intersil Americas Inc. 2003, 2005, 2007. All Rights Reserved.
/t
|
F
May 2, 2007
-t
Intersil (and design) is a registered trademark of Intersil Americas Inc.
at 2000pF C
OFF
EL7156CN
EL7156CN Z
7156CS
7156CS
7156CS
7156CSZ
7156CSZ
7156CSZ
prop delay mismatch
MARKING
PART
LOAD
TAPE &
REEL
13”
13”
7”
7”
-
-
-
-
8 Ld PDIP
8 Ld PDIP*
(Pb-free)
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
(Pb-free)
8 Ld SOIC
(Pb-free)
PACKAGE
EL7156
FN7280.3
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
DWG. #
PKG.

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el7156 Summary of contents

Page 1

... The isolation of the output FETs from the power supplies enables VH and set independently, enabling level-shifting to be implemented. Related to the EL7155, the EL7156 adds a lower supply pin VS- and makes VL an isolated and independent input. This feature adds applications flexibility and improves switching response due to the increased enhancement of the output FETs ...

Page 2

... Mismatch dΔ d-1 d-2 t Three-state Delay Enable d-3 t Three-state Delay Disable d-4 2 EL7156 Thermal Information = +25°C) Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C - -0.3V, V +0.3V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125° Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only ...

Page 3

... Mismatch RFΔ Turn-Off Delay Time d-1 t Turn-On Delay Time d Mismatch dΔ d-1 d-2 t Three-state Delay Enable d-3 t Three-state Delay Disable d-4 3 EL7156 = +5V -5V -5V +25°C, unless otherwise specified. (Continued CONDITION -200mA OUT I = +200mA OUT OE = 0V, OUT = V ...

Page 4

... T = +25° SUPPLY VOLTAGE (V) FIGURE 5. RISE/FALL TIME vs SUPPLY VOLTAGE 4 EL7156 MAX T = +125°C J 100 125 150 FIGURE 2. INPUT THRESHOLD vs SUPPLY VOLTAGE + S 15 FIGURE 4. “ON”-RESISTANCE vs SUPPLY VOLTAGE +25°C 1.8 HIGH THRESHOLD 1 ...

Page 5

... 15V FREQUENCY (Hz) FIGURE 11. SUPPLY CURRENT vs FREQUENCY 5 EL7156 (Continued) 15 FIGURE 8. PROPAGATION DELAY vs TEMPERATURE 10000 FIGURE 10. SUPPLY CURRENT vs LOAD CAPACITANCE 10V += 10M C ...

Page 6

... Three-state V Three-state Three-state Output 5V INPUT 2.5V 0 90% OUTPUT 10 0.1µ GND 4 5 EL7156 PIN MIN - to GND - GND ...

Page 7

... IN Input 4 GND Ground 5 VS- Negative Supply Voltage 6 VL Lower Output Voltage 7 OUT Output 8 VH High Output Voltage Block Diagram GND EL7156 FUNCTION OE THREE- LEVEL STATE SHIFTER CONTROL EQUIVALENT CIRCUIT INPUT CIRCUIT 1 Reference Circuit ...

Page 8

... VS+ and VS- pins, but VH must be greater than VL in order to prevent turning on the body diode at the output stage. The EL7156 is available in both the 8 Ld SOIC and the 8 Ld PDIP packages. The relevant package should be chosen depending on the calculated power dissipation. ...

Page 9

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 EL7156 ...

Page 10

... Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 10 EL7156 D (N/2)+1 (N/2) H ...

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