el7585il-t7 Intersil Corporation, el7585il-t7 Datasheet - Page 14

• Manufacturer Part Number: el7585il-t7
• Description: Tft-lcd Power Supply
• Manufacturer: Intersil Corporation

Discontinuous/Continuous Boost Operation and
its Effect on the Charge Pumps
The EL7585 V
edges to drive diode charge pumps from which LDO
regulators generate the V
appreciated that should a regular supply of LX switching
edges be interrupted, for example during discontinuous
operation at light A
affect the performance of V
depending on their exact loading conditions at the time.
To optimize V
discontinuous/continuous operation of the boost converter
can be adjusted, by suitable choice of inductor given V
V
be in continuous operation.
The following equation gives the boundary between
discontinuous and continuous boost operation. For
continuous operation (LX switching every clock cycle) we
require that:
I(A
where the duty cycle, D = (A
For example, with V
12V we find continuous operation of the boost converter can
be guaranteed for:
L = 10µH and I(A
L = 6.8µH and I(A
L = 3.3µH and I(A
Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
C
where f
Start-Up Sequence
Figure 26 shows a detailed start-up sequence waveform. For
a successful power-up, there should be six peaks at V
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
If EN is L, the device is powered down. If EN is H, and the
input voltage (V
starts to charge C
ramp followed by a slow ramp. If EN is low at this point, the
C
The first four ramps on C
initialize the fault protection switch and to check whether
there is a fault condition on C
OUT
OUT
DLY
VDD
, switching frequency and the A
≥
ramp will be delayed until EN goes high.
_load) > D*(1-D)*V
OSC
------------------------------------------------------
2
×
V
RIPPLE
is the switching frequency.
ON
ON
I
OUT
DD
/V
VDD
VDD
VDD
DLY
and V
) exceeds 2.5V, an internal current source
VDD
OFF
×
IN
) > 61mA
f
) > 89mA
) > 184mA
OSC
to an upper threshold using a fast
= 5V, F
regulation, the boundary of
boost load currents, then this may
OFF
DLY
ON
IN
ON
/(2*L*F
VDD
architecture uses LX switching
14
and V
DLY
(two up, two down) are used to
OSC
and V
- V
or V
= 1.0MHz and A
OSC
OFF
IN
OFF
VDD
REF
)/A
)
supplies. It can be
VDD
regulation -
current loading, to
. If a fault is
VDD
CDLY
IN
=
,
.
EL7585
detected, the outputs and the input protection will turn off
and the chip will power down.
If no fault is found, C
until the sequence is completed.
During the second ramp, the device checks the status of
V
PG output goes low and enables the input protection PMOS
Q1. Q1 is a controlled FET used to prevent in-rush current into
V
on is controlled by C
off and disconnect the inductor from V
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~V
enabled so V
diode. Hence, there is a step at V
start-up sequence. If this step is not desirable, an external
PMOS FET can be used to delay the output until the boost is
enabled internally. The delayed output appears at A
For EL7585, V
of the third ramp. The soft-start ramp depends on the value
of the C
is ~2ms.
V
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q4 to generate a delayed V
V
PG, V
Fault Protection
During the startup sequence, prior to BOOST soft-start,
V
device temperature is checked. If either of these are not
within the expected range, the part is disabled until the
power is recycled or EN is toggled.
If C
while if C
occur and the sequence will not complete.
Once the start-up sequence is completed, the chip
continuously monitors C
FBB and PG and checks for faults. During this time, the
voltage on the C
fault is detected, or the EN pin is pulled low.
A fault on C
chip immediately. If a fault on any other output is detected,
C
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the C
REF
BOOST
OFF
ON
REF
DELAY
DELAY
is enabled at the beginning of the sixth ramp. A
OFF
and over temperature. At the peak of the second ramp,
turns on at the start of the fourth peak. At the fifth
is checked to be within ±20% of its final value and the
DLY
will ramp up linearly with a 5µA (typical) current to
before V
DELAY
, DELB and V
is shorted low, then the sequence will not start,
DELAY
capacitor. For C
BOOST
BOOST
DLY
is shorted H, the first down ramp will not
BOOST
, V
o
DLY
rises to V
capacitor remains at 1.15V until either a
CDLY
REF
. When a fault is detected, M1 will turn
and V
ON
DLY
capacitor returns to 1.15V.
is enabled internally. Its rate of turn
or temperature will shut down the
continues ramping up and down
are checked at end of this ramp.
, DELB, FBP, FBL, FBN, V
LOGIC
DLY
IN
-V
BOOST
of 220nF, the soft-start time
DIODE
IN
soft-start at the beginning
. Initially the boost is not
IN
.
during this part of the
through the output
BOOST
VDD
March 9, 2006
output.
VDD
FN7345.2
REF
.
,
,