s1s65000 Epson Electronics America, Inc., s1s65000 Datasheet - Page 5

• Manufacturer Part Number: s1s65000
• Description: Network Camera Controller With Jpeg Encoder
• Manufacturer: Epson Electronics America, Inc.

MWE0#
MWE1#
MCLK
MCLKEN
MRAS#
MCAS#
MDQML
MDQMH
MII_TXCLK
MII_TXEN
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_RXCLK
MII_COL
MII_CRS
MII_RXDV
Pin Name
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
BLNC4
BLNC4
BLNC4
BLNC4
BLNC4
BLNC4
BLNC4
BLNC4
BLNC4
BLNC4
OLN4
OLN4
OLN4
OLN4
OLN4
OLN4
OLN4
Type
Cell
Pin No.
41-42
13
14
17
16
19
20
53
52
47
48
49
51
57
46
45
58
EPSON
This pin has the following functions (Low active):
" MWE0#: Write enable signal for memory (for static memory)
" CFWE# output
Write Enable signal for memory (for SDRAM)
Clock output signal for SDRAM
Clock enable signal for SDRAM
RAS signal for SDRAM (Low active)
CAS signal for SDRAM (Low active)
These pins have the following functions:
" Byte enable signal (for static memory)
" DQM signal for SDRAM
This pin has the following functions:
" MII_TXCLK: Clock TXCLK input for transmit data from Media
" GPIOF7 input/output
This pin has the following functions:
" MII_TXEN: Transmit output enable TXEN output to MII PHY
" GPIOF6 input/output
" SPI2_SCLK: Serial clock for SPI2 (Select “Function 2”)
This pin has the following functions:
" MII_TXD3: Transmit data TXD3 output to MII PHY
" GPIOF2 input/output
" SPI1_SCLK: Serial clock for SPI1 (Select “Function 2”)
This pin has the following functions:
" MII_TXD2: Transmit data TXD2 output to MII PHY
" GPIOF3 input/output
" SPI1_MOSI: Master Out/Slave In for SPI1 (Select “Function 2”)
This pin has the following functions:
" MII_TXD1: Transmit data TXD1 output to MII PHY
" GPIOF4 input/output
" SPI2_SS: Chip select signal for SPI2 (Select “Function 2”)
This pin has the following functions:
" MII_TXD0: Transmit data TXD0 output to MII PHY
" GPIOF5 input/output
" SPI2_MOSI: Master Out/Slave In for SPI2 (Select “Function 2”)
This pin has the following functions:
" MII_RXCLK: Receive data clock RXCLK input from MII PHY
" GPIOG1 input/output
This pin has the following functions:
" MII_COL: Collision detection COL input from MII PHY
" GPIOF1 input/output
" SPI1_MISO: Master In/Slave Out for SPI1 (Select “Function 2”)
This pin has the following functions:
" MII_CRS: Carrier sense CRS input from MII PHY
" GPIOF0 input/output
" SPI1_SS: Chip select signal for SPI1 (Select “Function 2”)
This pin has the following functions:
" MII_RXDV: Receive data valid RXDV input from MII PHY
" GPIOG2 input/output
(Default pin function)
(Low active)
During the CF cycle, this signal becomes write enable signal for CF
common memory or attribute space access.
Outputs the same frequency as the Internal Operating Frequency
(CPUCLK).
MDQML and MDQMH correspond to lower byte and higher byte
respectively.
Independent Interface Ethernet PHY (hereafter referred to as MII PHY)
(Default pin function, “Function 1”)
(Default pin function, “Function 1”)
(Default pin function, “Function 1”)
(Default pin function, “Function 1”)
(Default pin function, “Function 1”)
(Default pin function, “Function 1”)
(Default pin function, “Function 1”)
(Default pin function, “Function 1”)
(Default pin function, “Function 1”)
(Default pin function, “Function 1”)
Description
S1S65000
5