at91sam9xe256 ATMEL Corporation, at91sam9xe256 Datasheet
at91sam9xe256
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at91sam9xe256 Summary of contents
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... Additional Embedded Memories – One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32 Kbyte (for AT91SAM9XE256 and AT91SAM9XE512 Kbyte (for AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed – 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128, AT91SAM9XE256 or AT91SAM9XE512 Respectively ...
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Reset Controller (RSTC) – Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control • Clock Generator (CKGR) – Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing ...
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IEEE • Required Power Supplies: – 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL – 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) – 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or ...
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AT91SAM9XE128/256/512 Block Diagram The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-PQFP package and the unavailable pins are highlighted in on PIO Controller A” on page PIO Controller C” ...
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Figure 2-1. AT91SAM9XE128/256/512 Block Diagram 6254AS–ATARM–14-Feb-08 AT91SAM9XE128/256/512 Preliminary Filter 5 ...
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Signals Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP0 Peripherals I/O Lines Power Supply VDDIOP1 Peripherals I/O Lines Power Supply VDDBU Backup I/O Lines Power Supply VDDANA Analog Power ...
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Table 3-1. Signal Description List (Continued) Signal Name Function Flash and NVM Configuration Bits ERASE Erase Command NRST Microcontroller Reset TST Test Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ2 External Interrupt Inputs FIQ Fast ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NANDCS NAND Flash Chip Select NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDCS SDRAM Controller Chip Select BA0 - BA1 Bank ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A TIOBx TC Channel x I/O Line B SPIx_MISO Master In Slave Out SPIx_MOSI Master Out Slave In ...
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Table 3-1. Signal Description List (Continued) Signal Name Function ISI_D0-ISI_D11 Image Sensor Data ISI_MCK Image sensor Reference clock ISI_HSYNC Image Sensor Horizontal Synchro ISI_VSYNC Image Sensor Vertical Synchro ISI_PCK Image Sensor Data clock AD0-AD3 Analog Inputs ADVREF Analog Positive Reference ...
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Package and Pinout The AT91SAM9XE128/256/512 is available in a 208-pin PQFP Green package (0.5mm pitch 217-ball LFBGA Green package (0.8 mm ball pitch). 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given ...
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PQFP Package Pinout Table 4-1. Pinout for 208-pin PQFP Package Pin Signal Name Pin 1 PA24 53 2 PA25 54 3 PA26 55 4 PA27 56 5 VDDIOP0 57 6 GND 58 7 PA28 59 8 PA29 60 ...
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LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Character- istics” of the product datasheet. Figure 4-2. 6254AS–ATARM–14-Feb-08 AT91SAM9XE128/256/512 Preliminary shows the orientation of the 217-ball LFBGA package. 217-ball LFBGA Package ...
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LFBGA Package Pinout Table 4-2. Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 CFIOW/NBS3/NWR3 D5 A2 NBS0/ NWR2/NBS2/ A11 D10 A7 A13 D11 A8 BA0/A16 D12 ...
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Table 4-2. Pinout for 217-ball LFBGA Package (Continued) Pin Signal Name RAS Power Considerations 5.1 Power Supplies The AT91SAM9XE128/256/512 has several types of power supply pins: • VDDCORE pins: Power the core, including the ...
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The maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (control, address and data signals) do not exceed ...
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This pin is debounced on the RC oscillator or 32,768 Hz to improve the glitch tolerance. Mini- mum debouncing time is 200 ms. 6.5 PIO Controllers All the I/O lines are Schmitt trigger inputs and all the lines managed by ...
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Processor and Architecture 7.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • ...
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Round-Robin Arbitration, either with no default master, last accessed default master • Burst Management – Breaking with Slot Cycle Limit Support – Undefined Burst Length Support • One Address Decoder provided per Master – Three different slaves may be ...
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Masters to Slaves Access All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply ...
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SPI1 Transmit Channel – SPI0 Transmit Channel – SSC Transmit Channel – TWI0 Receive Channel – TWI1 Receive Channel – DBGU Receive Channel – USART4 Receive Channel – USART3 Receive Channel – USART2 Receive Channel – USART1 Receive Channel ...
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Memories Figure 8-1. AT91SAM9XE128/256/512 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 ...
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... Single Cycle Access at full matrix speed • Fast SRAM – Single Cycle Access at full matrix speed • 128 KB Embedded Flash 8.1.2 AT91SAM9XE256 • ROM – Single Cycle Access at full matrix speed • Fast SRAM – Single Cycle Access at full matrix speed • ...
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TST pin and PA0 to PA2 pins. tents of the ROM and the program available at address zero. Figure 8-2. ROM Boot Memory Map 0x0000 0000 SAM-BA Program FFPI Program 0x0000 7FFF ROM ...
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Communication through the DBGU supports a wide range of crystals from MHz via software auto-detection. • Communication through the USB Device Port is depends on crystal selected: – limited to an 18,432 Hz crystal if the ...
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Figure 8-3. Flash First Memory Plane Mapping 0x0020 0000 Locked Regions Area 128, 256 or 512 Kbytes 256, 512 or 1024 Pages 0x0021 FFFF or 0x0023 FFFF or 0x0027 FFFF 8.1.5.3 GPNVM Bits The AT91SAM9XE128/256/512 features four GPNVM bits that ...
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Non-volatile Brownout Detector Control Two GPNVM bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state. • GPNVMBit[1] is used as a brownout detector enable ...
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GPNVMBit[ Boot on Internal Flash • Boot on slow clock (On-chip RC or 32,768 Hz) The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz, the user must ...
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SDRAM Controller • Supported devices: – Standard and Low Power SDRAM (Mobile SDRAM) • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit ...
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System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure ...
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System Controller Block Diagram Figure 9-1. AT91SAM9XE128/256/512 System Controller Block Diagram periph_irq[2..24] efc2_irq pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset BOD VDDCORE VDDCORE POR NRST VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSCSEL SLOW XIN32 CLOCK ...
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Reset Controller • Based on two Power-on reset cells – One on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software • Controls the internal resets ...
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Clock Generator • Embeds a low power 32,768 Hz slow clock oscillator and a low-power RC oscillator selectable with OSCSEL signal – Provides the permanent slow clock SLCK to the system • Embeds the main oscillator – Oscillator bypass ...
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Idle Mode, processor stopped waiting for an interrupt – Slow Clock Mode, processor and peripherals running at low frequency – Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, – Backup Mode, Main Power Supplies ...
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Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved ...
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Chip Identification • Chip ID: – 0x3299A3A0 for the SAM9XE512 – 0x329A93A0 for the SAM9XE256 – 0x329973A0 for the SAM9XE128 • JTAG ID: 05B1_C03F • ARM926 TAP ID: 0x0792603F AT91SAM9XE128/256/512 Preliminary 36 6254AS–ATARM–14-Feb-08 ...
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Peripherals 10.1 User Interface The Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map ...
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Peripheral Interrupts and Clock Control 10.2.1.1 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-time ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 SPI0_MISO PA1 SPI0_MOSI PA2 SPI0_SPCK PA3 SPI0_NPCS0 PA4 RTS2 PA5 CTS2 PA6 MCDA0 PA7 MCCDA PA8 MCCK PA9 MCDA1 PA10 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A Peripheral B PB0 SPI1_MISO TIOA3 PB1 SPI1_MOSI TIOB3 PB2 SPI1_SPCK TIOA4 PB3 SPI1_NPCS0 TIOA5 PB4 TXD0 PB5 RXD0 PB6 TXD1 TCLK1 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 PC1 (1) PC2 (1) PC3 PC4 A23 PC5 A24 PC6 TIOB2 PC7 TIOB1 PC8 NCS4/CFCS0 PC9 NCS5/CFCS1 PC10 A25/CFRNW PC11 ...
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Embedded Peripherals 10.4.1 Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, ...
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IrDA modulation and demodulation – Communication 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.4.4 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs ...
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USB Host Port • Compliance with Open HCI Rev 1.0 Specification • Compliance with USB V2.0 Full-speed and Low-speed Specification • Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices • Root hub integrated with two downstream USB ...
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Preview scaler to generate smaller size image 10.4.11 Analog-to-digital Converter • 4-channel ADC • 10-bit 312K samples/sec. Successive Approximation Register ADC • -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity • Individual enable and disable of each ...
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Package Drawings Figure 11-1. 208-pin PQFP Package Drawing AT91SAM9XE128/256/512 Preliminary 46 6254AS–ATARM–14-Feb-08 ...
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Figure 11-2. 217-ball LFBGA Package Drawing 6254AS–ATARM–14-Feb-08 AT91SAM9XE128/256/512 Preliminary 47 ...
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... AT911SAM9XE128/256/512 Ordering Information Table 12-1. AT91SAM9XE128/256/512 Ordering Information Ordering Code AT91SAM9XE128-QU AT91SAM9XE128-CU AT91SAM9XE256-QU AT91SAM9XE256-CU AT91SAM9XE512-QU AT91SAM9XE512-CU AT91SAM9XE128/256/512 Preliminary 48 Package Package Type PQFP208 Green BGA217 Green PQFP208 Green BGA217 Green PQFP208 Green BGA217 Green Temperature Operating Range Industrial -40°C to 85°C Industrial -40°C to 85°C Industrial -40° ...
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Revision History Table 13-1. Document Ref. Comments 6254AS First issue. 6254AS–ATARM–14-Feb-08 AT91SAM9XE128/256/512 Preliminary Change Request Ref. 49 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. ARM ® or trademarks of ARM Ltd. Windows and others are the registered trademarks of Microsoft Corporation in the US and/or other countries ...