lpc1778 NXP Semiconductors, lpc1778 Datasheet - Page 87

• Manufacturer Part Number: lpc1778
• Description: 32-bit Arm Cortex-m3 Microcontroller; Up To 512 Kb Flash And 96 Kb Sram; Usb Device/host/otg; Ethernet; Lcd; Emc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178x_7x
Objective data sheet
11.5 I/O pins
11.6 SSP interface
Table 17.
T
[1]
Table 18.
[1]
[2]
[3]
[4]
Symbol
t
t
Symbol
T
T
SSP master
t
t
t
t
SSP slave
t
t
t
t
r
f
DS
DH
v(Q)
h(Q)
DS
DH
v(Q)
h(Q)
amb
cy(PCLK)
cy(clk)
Applies to standard port pins and RESET pin.
T
T
SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in
the SSP clock prescale register).
T
T
T
=
cy(clk)
cy(clk)
amb
cy(clk)
amb
−
40
= −40 °C to 85 °C; V
= 25 °C; V
= (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f
is a function of the main clock frequency f
= 12 × T
°
Dynamic characteristic: I/O pins
Dynamic characteristics: SSP pins in SPI mode
C to +85
Parameter
PCLK cycle time
clock cycle time
data set-up time
data hold time
data output valid
time
data output hold
time
data set-up time
data hold time
data output valid
time
data output hold
time
Parameter
rise time
fall time
All information provided in this document is subject to legal disclaimers.
cy(PCLK)
DD
= 3.3 V.
°
C; V
.
Rev. 00.04 — 8 July 2010
DD(3V3)
DD(REG)(3V3)
Conditions
pin configured as
output
pin configured as
output
over specified ranges.
Conditions
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
= 3.0 V to 3.6 V.
[1]
main
main
, the SSP peripheral clock divider (SSPCLKDIV), the
[1]
[2]
[2]
[2]
[2]
[3][4]
[3][4]
[3][4]
[3][4]
. The clock cycle time derived from the SPI bit rate
32-bit ARM Cortex-M3 microcontroller
Min
<tbd>
<tbd>
<tbd>
<tbd>
-
<tbd>
<tbd>
<tbd>
-
-
Min
3.0
2.5
LPC178x/7x
Typ
-
-
Max
-
-
-
<tbd>
-
-
-
<tbd>
<tbd>
-
© NXP B.V. 2010. All rights reserved.
Max
5.0
5.0
87 of 112
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns