p87lpc778-01 NXP Semiconductors, p87lpc778-01 Datasheet
p87lpc778-01
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p87lpc778-01 Summary of contents
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... RC operation, wide operating voltage range, programmable port output configurations, selectable Schmitt trigger inputs, LED drive outputs, and a built-in Watchdog timer. The P87LPC778 is based on an accelerated 80C51 processor architecture that executes instructions at twice the rate of standard 80C51 devices ...
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... Philips Semiconductors 3. Ordering information Table 1: Ordering information Type number Package Name Description P87LPC778FDH TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm 9397 750 12378 Product data CMOS single-chip 8-bit microcontroller Rev. 01 — 31 March 2004 P87LPC778 Temperature range Version +85 C SOT360-1 © ...
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... DATA RAM PORT 2 PORT 1 PORT 0 KEYPAD INTERRUPT PROGRAMMABLE CPU CLOCK ON-CHIP CONFIGURABLE RC OSCILLATOR OSCILLATOR Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller UART TIMER 0, 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS A/D CONVERTER PULSE WIDTH MODULATOR POWER MONITOR (POWER-ON RESET, ...
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... The P87LPC778 does not support access to external data memory. However, the User Configuration Bytes are accessed via the MOVX instruction as if they were in external data memory. Rev. 01 — 31 March 2004 P87LPC778 ...
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... AD0 — A/D channel 0 input. CIN1A — Comparator 1 positive input A. AD1 — A/D channel 1 input. CMPREF — Comparator reference (negative) input. AD2 — A/D channel 2 input. CMP1 — Comparator 1 output. AD3 — A/D channel 3 input. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller 20 P0.1/CIN2B/PWM0 19 P0.2/CIN2A 18 P0.3/CIN1B/AD0 17 P0 ...
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... EPROM configuration). Ground reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Section 8.9 “I/O ports” Section 8.9 “I/O ports” for details. ...
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... CMP2 CIN2B CIN2A CIN1B AD0 CIN1A AD1 CMPREF AD2 CMP1 AD3 T1 CLKOUT/X2 X1 Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller TxD RxD T0 INT0 INT1 RST PWM1 PWM2 002aaa613 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. SCL SDA ...
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... Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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Table 3: Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H Bit address ADCON* A/D Control C0h AUXR1 Auxiliary Function Register A2h Bit address B* B register F0h CMP1 Comparator ...
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Table 3: Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. 2 I2CON* I C-bus control register D8h/RD D8h/WR 2 I2DAT I C-bus data register D9h/RD D9h/WR Bit address IEN0* Interrupt enable 0 A8h ...
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Table 3: Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address PSW* Program status word D0h PT0AD Port 0 digital input disable F6h Bit address SCON* Serial port control 98h SBUF Serial ...
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... Remark: Please refer to the P87LPC778 User’s Manual for a more detailed functional description. 8.1 Enhanced CPU The P87LPC778 uses an enhanced 80C51 CPU which runs at twice the speed of standard 80C51 devices. This means that the performance of the P87LPC778 running at 5 MHz is exactly the same as that of a standard 80C51 running at 10 MHz. ...
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... This bit is writable while ADCS and ADCI are 0. AADR1, 0 Along with AADR0, selects the A/D channel to be converted. These bits can only be written while ADCS and ADCI are 0. See Table 7. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Figure ADCI ...
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... This state exists for one machine cycle as an A/D conversion is completed. ADCON - AADR1, AADR0 A/D input selection A/D input selected AD0 (P0.3) AD1 (P0.4) AD2 (P0.5) AD3 (P0.6) Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Table © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Power-down and Idle modes. A/D accuracy is also affected by noise generated elsewhere in the application, power supply noise, and power supply regulation. Since the P87LPC778 power pins are also used as the A/D reference and supply, the power supply has a very direct affect ...
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... Wait for ADCI to be set. A,DAC0 ; Get A/D result. ADCI ; Clear the A/D completion flag. ADCON,#0fch ; Clear the A/D channel number. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Section 8.2 “Analog functions” © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Philips Semiconductors 8.5 Analog comparators Two analog comparators are provided on the P87LPC778. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be confi ...
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... CP1 Comparator 1 OE1 CO1 Change Detect CN1 CP2 Comparator 2 OE2 CO2 Change Detect CN2 Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller …continued CMP1 (P0.6) CMF1 Interrupt CMP2 (P0.0) 002aaa617 CMF2 Interrupt © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... CPn, CNn, OEn = CINnB COn CMPREF 002aaa623 CPn, CNn, OEn = CINnB COn V REF (1.23V) 002aaa625 CPn, CNn, OEn = Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller CINnA COn CMPn CMPREF 002aaa620 b. CPn, CNn, OEn = CINnA COn V REF (1.23 V) 002aaa622 d ...
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... The interrupt routine used for the comparator must clear the interrupt flag (CMF1 in this case) before returning. 8.6 Pulse width modulator The P87LPC778 contains four Pulse Width Modulated (PWM) channels which can generate pulses of programmable length and interval. The output for PWM0 is on P0.1, PWM1 on P1.6, PWM2 on P1.7 and PWM3 on P0.0. After chip reset the output of the each PWM channel is refl ...
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... CNSW7 CNSW6 CNSW5 CNSW4 CNSW1 - Counter shadow register 1 (address 0D2H) bit allocation Unused Unused Unused Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller CNSW3 CNSW2 CNSW1 CNSW0 Unused Unused Unused CNSW9 CNSW8 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... REGISTER REGISTER A>B A>B PWM3I PWM2I BPEN BKEN PWM3B 2:1 MUX PWM3 = CNSW – CPSWn + 1 Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller 10-BIT SHADOW 10-BIT SHADOW REGISTER REGISTER 10-BIT COMPARE 10-BIT COMPARE REGISTER REGISTER A>B A>B PWM1I PWM0I PWM2B PWM1B PWM0B ...
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... Product data CPSW05 CPSW04 CPSW15 CPSW14 CPSW25 CPSW24 CPSW35 CPSW34 CPSW29 CPSW28 Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller CPSW03 CPSW02 CPSW01 CPSW13 CPSW12 CPSW11 CPSW23 CPSW22 CPSW21 CPSW33 CPSW32 CPSW31 3 ...
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... PWM2 output is non-inverted. Output is a ‘1’ from the start of the cycle until compare; ‘0’ thereafter. 1 PWM2 output is inverted. Output is ‘0’ from the start of the cycle until compare; ‘1’ thereafter. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller ...
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... See BKEN 0 ‘Brake’ is never asserted. 1 ‘Brake’ is enabled (see PWM3B 0 PWM3 is LOW, when Brake is asserted. 1 PWM3 is HIGH, when Brake is asserted. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller 21 and 22 BKEN PWM3B PWM2B PWM1B PWM0B Table 22 below. Table 22 below ...
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... MIN LO time. In cases where the software responds within MIN HI + MIN LO) time, Timer I will ensure that the minimum time is met. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Description PWM2 is LOW, when Brake is asserted. PWM2 is HIGH, when Brake is asserted. ...
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... SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to the fact that read and write functions of this register are different. Testing of I2CON bits via the JB and JNB instructions is supported. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller 2 C-bus stop and start 2 C-bus frame is in progress ...
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... XSTP W Writing a ‘1’ to this bit causes a stop condition to be generated 2 C-bus to proceed on to another bit. Typically, the first Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller 2 C-bus service routine 2 C-bus will not go on © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... C-bus message, a service routine waits for ATN = 1. 2 C-bus interface will only drive the SDA line low when Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller 2 C-bus start condition is detected at a non-idle 2 C-bus stop condition is detected at a non-idle ...
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... Regarding software response time Because the P87LPC778 can run at 20 MHz, and because the I optimized for high-speed operation quite likely that an I sometimes respond to DRDY (which is set at a rising edge of SCL) and write I2DAT before SCL has gone low again. If XDAT were applied directly to SDA, this situation would produce an I this possibility because XDAT is applied to SDA only when SCL is low ...
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... The value for CT1 and CT0 is osc Table 30 also shows the machine cycle count for various settings of Table 30 2 C-bus interface is operating, Timer I is pre-loaded at every SCL transition with a Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller TIRUN - ...
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... Interrupts The P87LPC778 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P87LPC778’s many interrupt sources. The P87LPC778 supports interrupt sources. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts at once ...
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... It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level external interrupt is enabled when the P87LPC778 is put into Power-down or Idle mode, the interrupt will cause the processor to wake up and resume operation. ...
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... Fig 9. Interrupt sources, interrupt enables, and Power-down wake-up sources. 8.9 I/O ports The P87LPC778 has 3 I/O ports, port 0, port 1, and port 2. The exact number of I/O pins available depend upon the oscillator and reset options chosen. At least 15 pins of the P87LPC778 may be used as I/Os when a two-pin external oscillator and an external reset circuit are used pins may be available if fully on-chip oscillator and reset confi ...
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... The open drain port configuration is shown in 9397 750 12378 Product data 2 CPU CLOCK DELAY port latch data . The pulldown for this mode is the same as for the DD Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Figure 10 very strong ...
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... P1.2 and P1.3 are permanently configured as open drain outputs. They may be used as inputs by writing ones to their respective port latches. P1.5 may be used as a Schmitt trigger input if the P87LPC778 has been configured for an internal reset and is not using the external reset input function RST. ...
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... Every output on the P87LPC778 may potentially be used sink LED drive output. However, there is a maximum total output current for all ports which must not be exceeded ...
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... The P87LPC778 allows any or all pins of port enabled to cause this interrupt. Port pins are enabled by the setting of bits in the KBI register, as shown in Tables and 36. The Keyboard Interrupt Flag (KBF) in the AUXR1 register is set when any enabled pin is pulled LOW while the KBI interrupt function is active ...
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... Oscillator The P87LPC778 provides several user selectable oscillator options, allowing optimization for a range of needs from high precision to lowest possible cost. These are configured when the EPROM is programmed. Basic oscillator types that are supported include: low, medium, and high speed crystals, covering a range from 20 kHz to 20 MHz ...
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... The P87LPC778 supports a clock output function when either the on-chip RC oscillator or external clock input options are selected. This allows external devices to synchronize to the P87LPC778. When enabled, via the ENCLK bit in the P2M1 register, the clock output appears on the X2 / CLKOUT pin whenever the on-chip oscillator is running, including in Idle mode ...
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... For backward compatibility, the CLKR configuration bit allows setting the P87LPC778 instruction and peripheral timing to match standard 80C51 timing by dividing the CPU clock by two. Default timing for the P87LPC778 is 6 CPU clocks per machine cycle while standard 80C51 timing is 12 clocks per machine cycle. This division also applies to peripheral timing, allowing 80C51 code that is oscillator frequency and/or timer rate dependent. The CLKR bit is located in the EPROM confi ...
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... BOI bit in the AUXR1 register (AUXR1.5). The P87LPC778 allows selection of two Brownout levels: 2 3.8 V. When V drops below the selected voltage, the brownout detector triggers and remains active until V Detect causes a processor reset, that reset remains active as long as V below the Brownout Detect voltage ...
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... PCON register is set to indicate an initial power up condition. The POF flag will remain set until cleared by software. 8.12 Power reduction modes The P87LPC778 supports Idle and Power-down modes of power reduction. 8.12.1 Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated ...
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... Brown Out Flag. Set automatically when a brownout reset or interrupt has occurred. Also set at Power-on. Cleared by software. Refer to Section 8.11 “Power monitoring functions” on page 42 additional information. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller greater than 4 V. The LPEP bit (AUXR.4), less than ...
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... Reset The P87LPC778 has an active LOW reset input when configured for an external reset. A fully internal reset may also be configured which provides a reset when power is initially applied to the device. The Watchdog timer can act as an oscillator fail detect because it uses an independent, fully on-chip oscillator. ...
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... Philips Semiconductors Fig 18. Block diagram showing reset sources. 8.14 Timer/counters The P87LPC778 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer0 and Timer1. Both can be configured to operate either as timers or event counters (see Tables automatically toggle the T0 and/or T1 pins upon timer overflow has been added. ...
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... Timer/Counter controlled by the standard Timer0 control bits. TH0 is an 8-bit timer only, controlled by the Timer1 control bits (see text). Timer1 in this mode is stopped. 46 and 47). The GATE bit is in the TMOD register. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller ...
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... Mode 3 is provided for applications that require an extra 8-bit timer. With Timer0 in Mode 3, an P87LPC778 can look like it has three Timer/Counters. When Timer0 is in Mode 3, Timer1 can be turned on and off by switching it into and out of its own Mode 3 ...
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... C TLn (5-bits) control C C TLn (8-bits) control C C TLn (8-bits) control C reload THn (8-bits) Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller overflow THn interrupt TFn (8-bits) toggle Tn pin TnOE 002aaa637 overflow THn interrupt TFn (8-bits) toggle Tn pin TnOE ...
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... The P87LPC778 includes an enhanced 80C51 UART. The baud rate source for the UART is Timer1 for modes 1 and 3, while the rate is fixed in modes 0 and 2. Because CPU clocking is different on the P87LPC778 than on the standard 80C51, baud rate calculation is somewhat different. Enhancements over the standard 80C51 UART include Framing Error detection and automatic address recognition ...
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... Product data 48 and 49. This register contains not only the mode selection bits, SCON - Serial port control register (address 98H) bit allocation SM1 SM2 REN Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller 1 of the CPU clock ...
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... UART 2: 9-bit UART 3: 9-bit UART 1 + SMOD1 ----------------------------- - = CPU clock frequency 32 Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Table 50 Baud rate CPU clock/6 variable (see text) CPU clock/32 or CPU clock/16 variable (see text the CPU clock the CPU clock frequency. ...
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... Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller 256 – 19 3.6864 * 7.3728 * 7.3728 * 14.7456 * 11.0592 - * 14.7456 - * 18.4320 - - - - - - - ...
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... CMOS single-chip 8-bit microcontroller 9600 19.2 k 38.4 k 13.8240 - - * 14.7456 - - 15.6672 - - 16.5888 - - 17.5104 - - * 18.4320 - - 19.3536 - - Figure 23 shows a simplified functional diagram of the serial port in Rev. 01 — 31 March 2004 P87LPC778 …continued 57.6 k 115 Table 52 1 the CPU 6 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the P87LPC778 the baud rate is determined by the Timer1 overflow rate. Figure 24 associated timings for transmit receive. ...
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... If the value accepted during the first bit time is not ‘0’, the receive circuits 9397 750 12378 Product data 25 and 26 show a functional diagram of the serial port in Modes 2 and 3. The Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller © Koninklijke Philips Electronics N.V. 2004. All rights reserved. of the ...
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... The 9 bit mode requires that the 9th information bit is a ‘1’ to indicate that the received information is an address and not data. 9397 750 12378 Product data CMOS single-chip 8-bit microcontroller Rev. 01 — 31 March 2004 P87LPC778 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Example 2 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Example 2 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X Example 3 Slave 2 ...
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... INPUT SHIFT REGISTER SBUF 80C51 internal bus S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller SHIFT SEND SHIFT CLOCK SHIFT 0 RXD P3.0 alt input function S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... ...
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... SBUF SBUF read SBUF 80C51 INTERNAL BUS Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller SHIFT DATA SEND serial port interrupt SHIFT stop bit stop bit © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... DETECTOR load SBUF SBUF read SBUF 80C51 INTERNAL BUS Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller SHIFT DATA SEND serial port interrupt SHIFT TB8 stop bit RB8 stop bit © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... DETECTOR load SBUF SBUF read SBUF 80C51 INTERNAL BUS Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller SHIFT DATA SEND serial port interrupt SHIFT TB8 stop bit RB8 stop bit © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... CMOS single-chip 8-bit microcontroller Figure 27. 55 and 56. When the Watchdog function is enabled, WDS2 MUX (WDCON.2-0) 8 MSBs 20-BIT COUNTER CLEAR Rev. 01 — 31 March 2004 P87LPC778 watchdog reset watchdog interrupt WDTE (UCFG1.7) S WDOVF Q (WDCON.5) R 002aaa645 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Watchdog clock select. The Watchdog timer is clocked by CPU clock / 6 when WDCLK = 1 and by the Watchdog RC oscillator when WDCLK = 0. This bit is forced to 0 (using the Watchdog RC oscillator) if the WDTE configuration bit = 1. WDS[2:0] Watchdog rate select. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller WDRUN WDCLK WDS2 © ...
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... Set by software. Can only be cleared by Power-on or brownout reset. See modes” on page 43 SRST Software Reset. When set by software, resets the P87LPC778 hardware reset occurred. 0 This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register ...
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... P87LPC778 in an application board. The P87LPC778 contains three signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes designate the device as an P87LPC778 manufactured by Philips. The signature bytes may be read by the user program at addresses FC30h, FC31h and FC60h with the MOVC instruction, using the DPTR register for addressing ...
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... System configuration bytes A number of user configurable features of the P87LPC778 must be defined at power up and therefore cannot be set by the program after start of execution. Those features are configured through the use of two EPROM bytes that are programmed in the same manner as the EPROM program space. The contents of the two confi ...
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... Only security bit 1 programmed. Further EPROM programming is disabled. Security bit 2 may still be programmed. 1 Only security bit 2 programmed. This combination is not supported. 0 Both security bits programmed. All EPROM verification and programming are disabled. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller …continued ...
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... Table 66 “Limiting values” may cause permanent damage to the device. This is a stress rating only of this specification are not implied. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Min Max 55 +85 65 ...
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... 1 Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller [1] Min Typ Max - 1 0.5 - 0.2V DD 0.5 - 0.3V DD 0. ...
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... V or above and MHz or less are guaranteed to continue to execute instructions correctly osc = 2 not guaranteed 4 above and MHz or less are guaranteed to continue to execute instructions correctly osc = 4.0 V and f DD Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller [1] Min Typ Max 2.35 - 2.69 3.45 3.8 3 ...
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... A source impedance higher than this driving an A/D input may result in loss of precision and erroneous readings. 9397 750 12378 Product data Conditions [1][2][3] [1][7] [ 100 kHz ) is the difference between the actual step width and the ideal step width. See e Figure 28. Figure 28. Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Min Max ...
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... Product data (2) (5) (4) (3) 1 LSB (ideal (LSB ideal ) ). e Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller (1) 250 251 252 253 254 255 LSB = 256 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. gain offset error ...
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... MHz osc MHz osc [2] f RCOSC [3][4] f RCOSC [3] f RCOSC t XLXL t XHQX XHDX Valid Valid Valid Valid Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller Min Max 1 MHz MHz 2.5 +2 MHz 25 +25 ...
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... Product data CMOS single-chip 8-bit microcontroller 0 0 CHCL t CLCX t C Conditions Min - 0 [ < V < Rev. 01 — 31 March 2004 P87LPC778 t CHCX t CLCH 002aaa416 [1] Typ Max - 0 250 500 - © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Product data 2.5 scale (1) ( 0.30 0.2 6.6 4.5 0.65 0.19 0.1 6.4 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION © ...
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... Philips Semiconductors 14. Revision history Table 71: Revision history Rev Date CPCN Description 01 20040331 - Product data (9397 750 12378) 9397 750 12378 Product data CMOS single-chip 8-bit microcontroller Rev. 01 — 31 March 2004 P87LPC778 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Licenses Purchase of Philips I Rev. 01 — 31 March 2004 P87LPC778 CMOS single-chip 8-bit microcontroller 2 C components 2 Purchase of Philips I C components conveys a license 2 under the Philips’ ...
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... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 31 March 2004 Document order number: 9397 750 12378 P87LPC778 CMOS single-chip 8-bit microcontroller 8.12 Power reduction modes . . . . . . . . . . . . . . . . . 43 8.12.1 Idle mode ...