p87lpc778-01 NXP Semiconductors, p87lpc778-01 Datasheet - Page 13

• Manufacturer Part Number: p87lpc778-01
• Description: P87lpc778 Cmos Single-chip 8-bit 80c51 Microcontroller With 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
the A/D to stabilize. Prior to the beginning of an A/D conversion, one analog input pin
must be selected for conversion via the AADR1 and AADR0 bits. These bits cannot
be changed while the A/D is performing a conversion.
An A/D conversion is started by setting the ADCS bit, which remains set while the
conversion is in progress. When the conversion is complete, the ADCS bit is cleared
and the ADCI bit is set. When ADCI is set, it will generate an interrupt if the interrupt
system is enabled, the A/D interrupt is enabled (via the EAD bit in the IE1 register),
and the A/D interrupt is the highest priority pending interrupt.
When a conversion is complete, the result is contained in the register DAC0 and can
be read to get the ADC result. This value will not change until another conversion is
started. Before another A/D conversion may be started, the ADCI bit must be cleared
by software. The A/D channel selection may be changed by the same instruction that
sets ADCS to start a new conversion, but not by the same instruction that clears
ADCI.
The connections of the A/D converter are shown in
The ideal A/D result may be calculated as follows:
Table 4:
Bit addressable; Reset value: 00H
Table 5:
Result
Bit
7
6, 5
4
3
2
1, 0
Bit
Symbol
=
V
ADCON - A/D control register (address C0h) bit allocation
ENADC
ADCON - A/D control register (address C0h) bit description
Symbol
ENADC
-
ADCI
ADCS
RCCLK
AADR1, 0
IN
7
–
V
SS
Rev. 01 — 31 March 2004
------------------------- - round result to the nearest integer
V
6
-
Description
When ENADC = 1, the A/D is enabled and conversions may take
place. Must be set 10 microseconds before a conversion is started.
ENADC cannot be cleared while ADCS or ADCI are ‘1’.
Reserved for future use. Should not be set to ‘1’ by user programs.
A/D conversion complete/interrupt flag. This flag is set when an
A/D conversion is completed. This bit will cause a hardware
interrupt if enabled and of sufficient priority. Must be cleared by
software.
A/D start. Setting this bit by software starts the conversion of the
selected A/D input. ADCS remains set while the A/D conversion is
in progress and is cleared automatically upon completion. While
ADCS or ADCI are one, new start commands are ignored. See
Table
When RCCLK = 0, the CPU clock is used as the A/D clock. When
RCCLK = 1, the internal RC oscillator is used as the A/D clock.
This bit is writable while ADCS and ADCI are 0.
Along with AADR0, selects the A/D channel to be converted.
These bits can only be written while ADCS and ADCI are 0. See
Table
DD
255
–
6.
7.
V
SS
5
-
ADCI
4
CMOS single-chip 8-bit microcontroller
ADCS
Figure
3
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
RCCLK
5.
P87LPC778
2
AADR1
1
AADR0
13 of 79
0
(1)