c8051t602 Silicon Laboratories, c8051t602 Datasheet
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... Timer 0 + Timer 1 - Timer 2 VOLTAGE COMPARATOR CALIBRATED PRECISION INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 8051 CPU (25 MIPS) 12 DEBUG CIRCUITRY Copyright © 2007 by Silicon Laboratories C8051T600/1/2/3/4 16-bit PWM Rising / falling edge capture Frequency output Software timer UART PCA 256 B SRAM POR WDT C8051T60x ...
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C8051T600/1/2/3/4/5 2 Rev. 0.5 ...
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Table of Contents 1. System Overview.................................................................................................... 13 1.1. CIP-51™ Microcontroller Core.......................................................................... 16 1.1.1. Fully 8051 Compatible.............................................................................. 16 1.1.2. Improved Throughput ............................................................................... 16 1.1.3. Additional Features .................................................................................. 17 1.2. On-Chip Memory............................................................................................... 18 1.3. On-Chip Debug Circuitry and Code Development Options............................... 18 ...
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C8051T600/1/2/3/4/5 9.3. Interrupt Handler ............................................................................................... 70 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 71 9.3.2. External Interrupts .................................................................................... 71 9.3.3. Interrupt Priorities ..................................................................................... 71 9.3.4. Interrupt Latency ...................................................................................... 72 9.3.5. Interrupt Register Descriptions................................................................. 73 9.4. Power Management Modes .............................................................................. 78 ...
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Register ......................................................................................... 116 14.5.SMBus Transfer Modes.................................................................................. 117 14.5.1.Master Transmitter Mode ....................................................................... 117 14.5.2.Master Receiver Mode ........................................................................... 118 14.5.3.Slave Receiver Mode ............................................................................. 119 14.5.4.Slave Transmitter Mode ......................................................................... 120 14.6.SMBus Status Decoding................................................................................. 120 15. UART0.................................................................................................................... 123 15.1.Enhanced Baud Rate Generation................................................................... 124 ...
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C8051T600/1/2/3/4 OTES 6 Rev. 0.5 ...
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List of Figures 1. System Overview Figure 1.1. C8051T600/2/4 Block Diagram .............................................................. 15 Figure 1.2. C8051T601/3/5 Block Diagram .............................................................. 15 Figure 1.3. On-Chip Clock and Reset ...................................................................... 17 Figure 1.4. On-chip Memory Map (C8051T600/1 shown) ........................................ 18 Figure 1.5. Digital ...
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C8051T600/1/2/3/4/5 Figure 13.2. Port I/O Cell Block Diagram ................................................................. 97 Figure 13.3. Crossbar Priority Decoder with XBR0 = 0x00 ...................................... 98 Figure 13.4. Crossbar Priority Decoder with XBR0 = 0x44 ...................................... 99 14. SMBus Figure 14.1. SMBus Block Diagram ....................................................................... ...
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List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 14 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings .................................................................... 23 3. Global Electrical Characteristics Table 3.1. Global DC Electrical Characteristics ....................................................... 24 Table 3.2. Index to ...
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C8051T600/1/2/3/4/5 16. Timers 17. Programmable Counter Array Table 17.1. PCA Timebase Input Options ............................................................. 144 Table 17.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 145 Table 17.3. Watchdog Timer Timeout Intervals ..................................................... 153 18. Revision Specific Behavior 19. C2 ...
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List of Registers SFR Definition 5.1. TOFFH: Temperature Offset Measurement High Byte . . . . . . . . . 34 SFR Definition 5.2. TOFFL: Temperature Offset Measurement Low Byte . . . . . . . . . ...
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C8051T600/1/2/3/4/5 SFR Definition 16.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Code written for the C8051T600/1/2/3/4/5 family of processors will run on the C8051F300 Mixed-signal ISP Flash microcontroller, providing a quick, cost-effective way to develop code without requiring special emulator circuitry. The C8051T600/1/2/3/4/5 processors include Silicon Laboratories’ 2-Wire C2 Debug and Programming interface, which allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application ...
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... C8051T600/1/2/3/4/5 Table 1.1. Product Selection Guide C8051T600-GM 25 8k* 256 C8051T600-GS 25 8k* 256 C8051T601-GM 25 8k* 256 C8051T601-GS 25 8k* 256 C8051T602- 256 C8051T602- 256 C8051T603- 256 C8051T603- 256 C8051T604- 256 C8051T604- 256 C8051T605- 256 C8051T605- 256 ...
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CIP-51 8051 Controller Core 2k/4k/8k Byte OTP Power On Program Memory Reset Reset Debug / C2CK/RST 256 byte SRAM Programming Hardware SYSCLK C2D Power Net VDD External GND EXTCLK Clock Circuit System Clock Configuration Figure 1.1. C8051T600/2/4 Block Diagram CIP-51 ...
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C8051T600/1/2/3/4/5 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051T600/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. ...
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Additional Features The C8051T600/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripher- als to improve performance and ease of use in end applications. The extended interrupt handler provides 12 interrupt sources into the CIP-51, allowing ...
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... RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. The C8051T600/1 include EPROM program memory, the C8051T602/3 include 4 kB, and the C8051T604/5 include 2 kB. See Figure 1.4 for the C8051T600/1 system memory map. ...
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Programmable Digital I/O and Crossbar C8051T600/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins ...
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C8051T600/1/2/3/4/5 real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the system clock. Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software Timer, High Speed ...
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Analog to Digital Converter (C8051T600/2/4) The C8051T600/2/4 include an on-chip 10-bit SAR ADC with a 10-channel input multiplexer. With a maxi- mum throughput of 500 ksps, the ADC offers true 10-bit accuracy with an INL of ±1LSB. The ...
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C8051T600/1/2/3/4/5 1.8. Comparator C8051T600/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and config- ured via user software. All Port I/O pins may be configured as comparator inputs. Two comparator outputs may be routed to a Port pin if ...
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Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Ambient temperature under bias Storage Temperature Voltage on RST or any Port I/O Pin (except V during programming) with PP respect to GND Voltage on V with respect to GND ...
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C8051T600/1/2/3/4/5 3. Global Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter 1 Supply Voltage Digital Supply Current with CPU Active V Digital Supply Current with CPU Inac- tive ...
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Table 3.2. Index to Electrical Characteristics Tables Table Title ADC0 Electrical Characteristics External Voltage Reference Circuit Electrical Characteristics Comparator0 Electrical Characteristics Reset Electrical Characteristics EPROM Electrical Characteristics Internal Oscillator Electrical Characteristics Port I/O DC Electrical Characteristics C8051T600/1/2/3/4/5 Rev. 0.5 Page ...
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C8051T600/1/2/3/4/5 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051T600/1/2/3/4/5 Pin Number Pin Number Name QFN-11 SOIC- VREF / ...
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VREF / P0.0 P0.1 VDD VPP / P0.2 EXTCLK / P0.3 Figure 4.1. QFN-11 Pinout Diagram (Top View) C8051T600/1/2/3/4/5 CNVSTR GND Rev. 0.5 C2D / P0.7 P0.6 / C2CK / /RST P0.5 P0.4 27 ...
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C8051T600/1/2/3/4/5 Bottom View Side E View e Side D View e Figure 4.2. QFN-11 Package Drawing 28 Table 4.2. QFN-11 Package Dimensions E3 Min A 0. — b 0.18 ...
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TOP VIEW P0.6 1 C2D/P0.7 2 GND 3 N/C 4 P0.0 5 P0.1 6 VDD 7 Figure 4.3. SOIC-14 Pinout Diagram (Top View) Rev. 0.5 C8051T600/1/2/3/4/5 C2CK/RST 14 P0.5 13 P0.4 12 N/C 11 P0.3 10 N/C 9 P0.2/VPP 8 ...
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C8051T600/1/2/3/4 PIN 1 1 IDENTIFIER Top View A2 b Side View Figure 4.4. SOIC-14 Package Drawing 30 Table 4.3. SOIC-14 Package ...
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ADC0 - 10-Bit SAR ADC (C8051T600/2/4 Only) The ADC0 subsystem for the C8051T600/2/4 devices consists an analog multiplexer (referred to as AMUX0) with 10 input selection options, a gain stage programmable 0.5x, and a 500 ksps, ...
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C8051T600/1/2/3/4/5 5.1. Analog Multiplexer The analog multiplexer (AMUX0) selects the positive input to the ADC, allowing any Port pin to be mea- sured relative to GND. Additionally, the on-chip temperature sensor or the positive power supply (V may be selected ...
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Temperature Sensor The temperature sensor transfer function is shown in Figure 5.2. The output voltage (V input when the temperature sensor is selected by bits AMX0P2–0 in register AMX0SL. Values for the Off- set and Slope parameters can be ...
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C8051T600/1/2/3/4/5 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (V SFR Definition 5.1. TOFFH: Temperature Offset Measurement High Byte R/W R/W R/W TOFF9 TOFF8 TOFF7 Bit7 Bit6 ...
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SFR Definition 5.2. TOFFL: Temperature Offset Measurement Low Byte R/W R/W R/W TOFF1 TOFF0 — Bit7 Bit6 Bit5 Bits7–6: Bits 1-0 of temperature sensor offset measurement. Bits5–0: Read: 000000b, Write = Don’t Care The temperature sensor offset measurement is taken ...
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C8051T600/1/2/3/4/5 5.6. Modes of Operation ADC0 has a maximum sampling rate of 500 ksps. The ADC0 SAR clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC ...
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Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left at ...
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C8051T600/1/2/3/4/5 5.6.3. Settling Time Requirements A minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, ...
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SFR Definition 5.3. AMX0SL: AMUX0 Channel Select R/W R/W R Bit7 Bit6 Bit5 Bits7–4: Unused. Bits3–0: AMX0P3–0: AMUX0 Positive Input Selection. 0000–1001b: ADC0 Positive Input selected per the chart below. 1010–1111b: RESERVED. AMX0P3–0 0000 0001 0010 0011 ...
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C8051T600/1/2/3/4/5 SFR Definition 5.4. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to ...
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SFR Definition 5.7. ADC0CN: ADC0 Control R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active ...
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C8051T600/1/2/3/4/5 5.7. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an inter- rupt-driven system, saving code space ...
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SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: ADC0 Greater-Than High Byte. SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: ADC0 Greater-Than Low Byte. In 8-bit ...
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C8051T600/1/2/3/4/5 Table 5.1. ADC0 Electrical Characteristics 2.50 V (REFSL = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified. DD REF Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic ...
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Voltage Reference Options The voltage reference MUX is configurable to use an externally connected voltage reference, the unregu- lated power supply voltage ( the regulated 1.8 V internal supply (see Figure 6.1). The REFSL bit in DD ...
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C8051T600/1/2/3/4/5 SFR Definition 6.1. REF0CN: Reference Control R/W R/W R/W — — — Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bit4: REGOVR: Regulator Reference Override. This bit “overrides” the REFSL bit, and allows the internal ...
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Comparator0 C8051T600/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous ...
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C8051T600/1/2/3/4/5 The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the system clock; the ...
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Comparator0 rising-edge interrupt. Once set, these bits remain set until cleared by software. The output state of Comparator0 can be obtained at any time by reading the CP0OUT bit. Comparator0 is enabled by setting the CP0EN bit to logic 1, ...
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C8051T600/1/2/3/4/5 SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection R/W R/W R/W — — CMX0N1 CMX0N0 Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bits6–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin ...
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SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R/W — — — Bit7 Bit6 Bit5 Bits7–2: UNUSED. Read = 000000b, Write = don’t care. Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select. These bits select the response time and power consumption for ...
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C8051T600/1/2/3/4/5 Table 7.1. Comparator0 Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise specified. DD Parameter CP0+ – CP0– = 100 mV Response Time: Mode 0, Vcm* = 1.5 V CP0+ – CP0– = –100 mV CP0+ ...
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Voltage Regulator (REG0) C8051T600/1/2/3/4/5 devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a V supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to DD ...
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C8051T600/1/2/3/4/5 SFR Definition 8.1. REG0CN: Voltage Regulator Control R/W R/W R/W STOPCF BYPASS — Bit7 Bit6 Bit5 Bit 7 STOPCF: Stop Mode Configuration. This bit configures the regulator’s behavior when the device enters STOP mode. 0: Regulator is still active ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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C8051T600/1/2/3/4/5 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, ...
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Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ...
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C8051T600/1/2/3/4/5 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Logical Operations ANL A, Rn AND Register to A ANL A, direct AND direct byte to A ANL A, @Ri AND indirect RAM to A ANL A, #data AND immediate ...
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Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description *MOVX A, @DPTR Move external data (16-bit address *MOVX @DPTR, A Move A to external data (16-bit address) PUSH direct Push direct byte onto stack POP direct Pop direct ...
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C8051T600/1/2/3/4/5 Notes on Registers, Operands and Addressing Modes: Rn —Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel —8-bit, signed (two’s complement) offset relative to the first byte of the following ...
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... Note: 512 bytes (0x1E00 – 0x1FFF) of this memory are reserved for factory use and are not available for user program storage. The C8051T602/3 implements 4096 bytes of OTP EPROM pro- gram memory space; the C8051T604/5 implements 2048 bytes of OTP EPROM program memory space. ...
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C8051T600/1/2/3/4/5 9.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. ...
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Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 ...
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C8051T600/1/2/3/4/5 Table 9.2. Special Function Register (SFR) Memory Map F8 CPT0CN PCA0L PCA0H F0 B P0MDIN E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 E0 ACC XBR0 XBR1 D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 D0 PSW REF0CN C8 TMR2CN TMR2RLL TMR2RLH C0 ...
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Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High Byte ADC0GTL 0xC3 ...
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C8051T600/1/2/3/4/5 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description PCA0CPM2 0xDC PCA Module 2 Mode Register PCA0H 0xFA PCA Counter High PCA0L 0xF9 PCA Counter Low PCON ...
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Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should only be set to the value indicated in the register description. Future product versions may use these bits to implement ...
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C8051T600/1/2/3/4/5 SFR Definition 9.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction). It ...
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SFR Definition 9.5. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 9. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 ...
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C8051T600/1/2/3/4/5 9.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 12 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific ...
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MCU Interrupt Sources and Vectors The MCUs support 12 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend- ing flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and ...
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C8051T600/1/2/3/4/5 9.3.4. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: ...
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Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the ...
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C8051T600/1/2/3/4/5 SFR Definition 9.8. IP: Interrupt Priority R/W R/W R PT2 Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer ...
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SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 R/W R/W R ECP0R Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt. This bit sets the masking of ...
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C8051T600/1/2/3/4/5 SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 R/W R/W R PCP0R Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 11b. Write = don’t care. Bit5: PCP0R: Comparator0 (CP0) Rising Interrupt Priority Control. This bit sets the priority ...
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SFR Definition 9.11. IT01CF: INT0/INT1 Configuration R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 16.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 ...
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C8051T600/1/2/3/4/5 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts ...
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Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital periph- ...
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C8051T600/1/2/3/4 OTES 80 Rev. 0.5 ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
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C8051T600/1/2/3/4/5 10.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low. An additional delay occurs before the device is released from reset; the delay decreases as the V ramp time ...
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Power-Fail Reset the power supply monitor is enabled, when a power-down transition or power irregularity causes V drop below V , the power supply monitor will drive the RST pin low and hold the CIP- ...
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... Table 10.1. User Code Space Address Limits Device C8051T600/1 C8051T602/3 C8051T604/5 The OTPERR bit (RSTSRC.6) is set following any OTP error reset. The state of the RST pin is unaffected by an OTP error reset. 10.8. Software Reset Software may force a reset by writing a ‘ ...
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SFR Definition 10.1. RSTSRC: Reset Source R R R/W - OTPERR C0RSEF Bit7 Bit6 Bit5 Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read- modify-write instructions read and ...
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C8051T600/1/2/3/4/5 Table 10.2. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Leakage Current V Ramp Time for POR DD V Monitor Threshold (V ...
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... One-Time Programmable Read-Only Memory C8051T600/1/2/3/4/5 devices include 8 kB (C8051T600/1 (C8051T602/3 (C8051T604/5) of on-chip One Time Programmable (OTP) EPROM for program code storage. The EPROM memory can be programmed via the C2 debug and programming interface when a special programming voltage is applied to the V pin. Table 11.1 shows the EPROM specifications. ...
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... C2 interface. C8051T600/1 Security Byte 0x1FFF 0x1FFE Reserved 0x1E00 0x1DFF 7680 Bytes OTP Memory 0x0000 Figure 11.1. OTP EPROM Program Memory Map 88 Description C8051T602/3 C8051T604/5 Security Byte Security Byte 0x1FFF 0x1FFE Reserved 0x1000 0x0FFF 4096 Bytes OTP Memory 2048 Bytes OTP Memory 0x0000 Rev ...
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Program Memory CRC A CRC engine is included on-chip which provides a means of verifying EPROM contents once the device has been programmed. The CRC engine is available for EPROM verification even if the device is fully read and ...
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C8051T600/1/2/3/4 OTES 90 Rev. 0.5 ...
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Oscillators All C8051T600/1/2/3/4/5 devices include a calibrated, precision internal oscillator and an external clock input circuit. The external clock input circuitry can be configured to operate from a CMOS clock, an exter- nal capacitor external RC circuit. ...
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C8051T600/1/2/3/4/5 SFR Definition 12.1. OSCICL: Internal Oscillator Calibration R/W R/W R/W - Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits6–0: OSCICL: Internal Oscillator Calibration Register. This register adjusts the internal oscillator period. The reset value ...
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External Oscillator Circuit The external oscillator circuit can accept an external CMOS clock, or operate from an external capacitor or RC circuit applied to the EXTCLK pin (P0.3). To operate in external CMOS mode, the EXTCLK pin should be ...
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C8051T600/1/2/3/4/5 SFR Definition 12.3. OSCXCN: External Oscillator Control R R/W R/W - XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: Unused. Read = 0, Write = don’t care. Bits6–4: XOSCMD2–0: External Oscillator Mode Bits. 00x: External Oscillator circuit off. 010: External ...
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External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 12.1, Option 2. The capacitor should be no greater than 100 pF; however, for very ...
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C8051T600/1/2/3/4 OTES 96 Rev. 0.5 ...
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Port Input/Output Digital and analog resources are available through a byte-wide digital I/O Port, Port0. Each of the Port pins can be defined as general-purpose I/O (GPIO), analog input, or assigned to one of the internal digital resources as ...
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C8051T600/1/2/3/4/5 13.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 13.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource ...
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SF Signals VREF PIN I TX0 RX0 SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI Port pin potentially available to peripheral Port pin skipped by CrossBar SF Signals Special Function Signals are not ...
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C8051T600/1/2/3/4/5 All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its ...
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SFR Definition 13.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W PCA0ME CP0AOEN CP0OEN SYSCKE SMB0OEN URX0EN UTX0EN 00000000 Bit7 Bit6 Bit5 Bits7–6: PCA0ME: PCA Module I/0 Enable Bits 00: All PCA I/O unavailable at Port pins. 01: CEX0 ...
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C8051T600/1/2/3/4/5 SFR Definition 13.3. XBR2: Port I/O Crossbar Register 2 R/W R/W R/W WEAKPUD XBARE - Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as push-pull). 1: ...
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SFR Definition 13.4. P0: Port0 R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7–0: P0.[7:0] Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers 0: Logic Low Output. 1: Logic High Output (open-drain if corresponding ...
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C8051T600/1/2/3/4/5 Table 13.1. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull Output High ...
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SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with the ...
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C8051T600/1/2/3/4/5 14.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version ...
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The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated ...
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C8051T600/1/2/3/4/5 14.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster ...
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Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control register) to find the cause of ...
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C8051T600/1/2/3/4/5 14.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the ...
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Timer Source Overflows SCL T Low Figure 14.4. Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is ...
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C8051T600/1/2/3/4/5 SFR Definition 14.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus ...
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SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 14.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...
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C8051T600/1/2/3/4/5 SFR Definition 14.2. SMB0CN: SMBus Control R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: ...
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Table 14.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: • A START is generated. MASTER • START is generated. • The SMBus interface enters transmitter mode TXMODE (after SMB0DAT is written before the start of an ...
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C8051T600/1/2/3/4/5 14.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...
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SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...
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C8051T600/1/2/3/4/5 14.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the ...
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Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and ...
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C8051T600/1/2/3/4/5 14.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START ...
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Table 14.4. SMBus Status Decoding Values Read Current SMbus State A master START was gen- 1110 erated. A master data or address byte was transmitted; NACK received. 1100 A master data or address 0 ...
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C8051T600/1/2/3/4/5 Table 14.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A slave address was received; ACK requested. 0010 Lost arbitration as master slave address received; ACK requested. Lost arbitration while 0010 0 ...
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UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “15.1. ...
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C8051T600/1/2/3/4/5 15.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...
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Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 15.3. Figure 15.3. UART Interconnect Diagram 15.2.1. 8-Bit UART ...
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C8051T600/1/2/3/4/5 15.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit ...
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Master Slave Device Device Figure 15.6. UART Multi-Processor Mode Interconnect Diagram C8051T600/1/2/3/4/5 Slave Slave Device Device Rev. 0.5 +5V 127 ...
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C8051T600/1/2/3/4/5 SFR Definition 15.1. SCON0: Serial Port 0 Control R/W R/W R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: Mode 0: 8-bit UART with Variable Baud ...
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SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB–LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is ...
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C8051T600/1/2/3/4/5 Table 15.1. Timer Settings for Standard Baud Rates Using the Internal 24.5 MHz Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% X ...
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Timers Each MCU includes 3 counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can ...
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C8051T600/1/2/3/4/5 Crossbar Decoder” on page 98 for information on selecting and configuring external I/O pins.) Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the sys- tem clock. When ...
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Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. ...
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C8051T600/1/2/3/4/5 16.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in ...
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SFR Definition 16.1. TCON: Timer Control R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared ...
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C8051T600/1/2/3/4/5 SFR Definition 16.2. TMOD: Timer Mode R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only ...
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SFR Definition 16.3. CKCON: Clock Control R/W R/W R/W - T2MH T2ML Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don’t care. Bit6: T2MH: Timer 2 High Byte Clock Select This bit selects the clock supplied to the ...
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C8051T600/1/2/3/4/5 SFR Definition 16.4. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0 SFR Definition 16.5. TL1: Timer 1 ...
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Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the ...
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C8051T600/1/2/3/4/5 16.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 16.5. TMR2RLL holds the reload value for TMR2L; ...
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SFR Definition 16.8. TMR2CN: Timer 2 Control R/W R/W R/W TF2H TF2L TF2LEN Bit7 Bit6 Bit5 Bit7: TF2H: Timer 2 High Byte Overflow Flag Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00 ...
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C8051T600/1/2/3/4/5 SFR Definition 16.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition ...
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Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module has ...
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C8051T600/1/2/3/4/5 17.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of ...
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Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function ...
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C8051T600/1/2/3/4/5 17.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/ timer and copy it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). ...
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Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and ...
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C8051T600/1/2/3/4/5 17.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, ...
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Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of ...
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C8051T600/1/2/3/4/5 17.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA ...
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Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod- ule defines the number of PCA clocks for the low time of the PWM signal. When ...
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C8051T600/1/2/3/4/5 17.3.1. Watchdog Timer Operation While the WDT is enabled: • PCA counter is forced on. • Writes to PCA0L and PCA0H are not allowed. • PCA clock source bits (CPS2–CPS0) are frozen. • PCA Idle control bit (CIDL) is ...
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Watchdog Timer Usage To configure the WDT, perform the following tasks: • Disable the WDT by writing a ‘0’ to the WDTE bit. • Select the desired PCA clock source (with the CPS2–CPS0 bits). • Load PCA0CPL2 with the ...
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C8051T600/1/2/3/4/5 17.4. Register Descriptions for PCA Following are detailed descriptions of the special function registers related to the operation of the PCA. SFR Definition 17.1. PCA0CN: PCA Control R/W R/W R — Bit7 Bit6 Bit5 Bit7: CF: PCA ...
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SFR Definition 17.2. PCA0MD: PCA Mode R/W R/W R/W CIDL WDTE WDLCK Bit7 Bit6 Bit5 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller ...
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C8051T600/1/2/3/4/5 SFR Definition 17.3. PCA0CPMn: PCA Capture/Compare Mode R/W R/W R/W PWM16n ECOMn CAPPn Bit7 Bit6 Bit5 PCA0CPMn Address: PCA0CPM0 = 0xDA ( PCA0CPM1 = 0xDB ( PCA0CPM2 = 0xDC ( Bit7: PWM16n: 16-bit ...
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SFR Definition 17.4. PCA0L: PCA Counter/Timer Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. SFR Definition 17.5. PCA0H: PCA Counter/Timer ...
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C8051T600/1/2/3/4/5 SFR Definition 17.6. PCA0CPLn: PCA Capture Module Low Byte R/W R/W R/W Bit7 Bit6 Bit5 PCA0CPLn Address: PCA0CPL0 = 0xFB ( PCA0CPL1 = 0xE9 ( PCA0CPL2 = 0xEB ( Bits7–0: PCA0CPLn: PCA Capture ...
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Revision Specific Behavior This chapter contains behavioral differences between C8051T60x "REV C" and behavior as stated in the data sheet. These deviations will be resolved in the next revision of the device. 18.1. Revision Identification The Lot ID Code ...
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C8051T600/1/2/3/4/5 18.2. SAR Clock Maximum The maximum SAR clock for "REV C" devices is slower than specified in the data sheet. On "REV C" devices, the maximum SAR clock for full-performance operation is 4 MHz. If the SAR clock is ...
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C2 Interface C8051T600/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow EPROM programming and in-system debugging with the production part installed in the end application. The C2 interface operates using only two pins: a bi-directional ...
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C8051T600/1/2/3/4/5 C2 Register Definition 19.2. DEVICEID: C2 Device ID Bit7 Bit6 Bit5 This read-only register returns the 8-bit device ID: 0x10. C2 Register Definition 19.3. REVID: C2 Revision ID Bit7 Bit6 Bit5 This read-only register returns the 8-bit revision ID: ...
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C2 Register Definition 19.6. EPDAT: C2 EPROM Data Bit7 Bit6 Bit5 Bits7–0: EPDAT: C2 EPROM Data Register This register is used to pass EPROM data during C2 EPROM operations. C2 Register Definition 19.7. EPADDRH: C2 EPROM Address High Byte Bit7 ...
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C8051T600/1/2/3/4/5 C2 Register Definition 19.9. CRC0: CRC Byte 0 Bit7 Bit6 Bit5 Bits7–0: CRC Byte 0. A write to this register initiates a 16-bit CRC of one 256-byte block of EPROM memory. The byte written to CRC0 is the upper ...
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C2 Register Definition 19.12. CRC3: CRC Byte 3 Bit7 Bit6 Bit5 Bits7–0: CRC Byte 3. See Section “11.3. Program Memory CRC” on page 89 C8051T600/1/2/3/4/5 Bit4 Bit3 Bit2 Bit1 Rev. 0.5 Reset Value 00000000 Bit0 0xAD C2ADD: . 165 ...
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C8051T600/1/2/3/4/5 19.2. C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and EPROM programming functions may be performed. This is possible because C2 communication is typi- cally performed when ...
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N : OTES C8051T600/1/2/3/4/5 Rev. 0.5 167 ...
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