c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 82

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

C8051T600/1/2/3/4/5
10.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low. An additional delay
occurs before the device is released from reset; the delay decreases as the V
ramp time is defined as how fast V
monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset delay (T
cally less than 0.3 ms. The maximum V
be released from reset before V
exceed 1 ms, external circuitry should be used to hold RST low until the V
ply range for the device.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory is undefined after a power-on reset. The V
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Logic HIGH
Logic LOW
TBD
TBD
TBD
TBD
Figure 10.2. Power-On and V
/RST
V
RST
DD
DD
reaches the V
Power-On
ramps from 0 V to 1.8 V). Figure 10.2. plots the power-on and V
Reset
DD
ramp time is 1 ms; slower ramp times may cause the device to
T
DD
PORDelay
Rev. 0.5
monitor is disabled following a power-on reset.
RST
DD
level. If the V
Monitor Reset Timing
Monitor
Reset
DD
VDD
ramp time in an application will
DD
supply is within the valid sup-
DD
ramp time increases (V
VDD
PORDelay
t
) is typi-
DD
DD